公开(公告)号：US11233520B2

公开(公告)日：2022-01-25

申请号：US17073181

申请日：2020-10-16

Applicant: Infineon Technologies AG ,  Politecnico Di Milano

Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

IPC: H03L7/24 ,  H03B5/12 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

公开(公告)号：US10826508B2

公开(公告)日：2020-11-03

申请号：US16189949

申请日：2018-11-13

Applicant: Infineon Technologies AG ,  Politecnico Di Milano

Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

IPC: H03L7/24 ,  H03B5/12 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

公开(公告)号：US10034258B2

公开(公告)日：2018-07-24

申请号：US15197331

申请日：2016-06-29

Applicant: Infineon Technologies AG

Inventor： Daniele Dal Maistro ,  Marc Tiebout

IPC: H04L1/20 ,  H04W56/00 ,  H04B7/06 ,  H04L5/00 ,  H04L1/24

Abstract: A signal detector device and method includes a quadrature demodulator configured to receive an input signal, a first reference signal, and a second reference signal in quadrature with the first reference signal, the quadrature demodulator further configured to produce a plurality of output signals from the input signal and the first and the second reference signal, the plurality of output signals indicating the amplitude and phase of the input signal, and one or more inverting circuits, the inverting circuits having a first and a second programmable output polarity, the plurality of output signals being output by the quadrature demodulator when the inverting circuits are set to the first programmable output polarity, the plurality of output signals being inverted and output by the quadrature demodulator when the inverting circuits are set to the second programmable output polarity.

公开(公告)号：US20210159594A1

公开(公告)日：2021-05-27

申请号：US16799089

申请日：2020-02-24

Applicant: Infineon Technologies AG

Inventor： Marc Tiebout ,  Daniele Dal Maistro ,  Ivan Tsvelykh ,  Samo Vehovc ,  Peter Pfann

IPC: H01Q3/26 ,  H04B17/12 ,  G01R29/10 ,  G01R29/08

Abstract: A calibration method for a phased array system comprises sequentially injecting a tone into a first plurality of antenna elements of an antenna array, receiving the tone by a second plurality of antenna elements of the antenna array through parasitic coupling between the first plurality of antenna elements and the second plurality of antenna elements, measuring a plurality of phase errors between the first plurality of antenna elements and the second plurality of antenna elements, populating a lookup table with the plurality of phase errors, and calibrating a plurality of phase shifters associated with a plurality of channels in the phased array system using the plurality of phase errors in the lookup table.

公开(公告)号：US10135452B2

公开(公告)日：2018-11-20

申请号：US15438438

申请日：2017-02-21

Applicant: Infineon Technologies AG ,  Politecnico Di Milano

Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

IPC: H03L7/24 ,  H03L7/099 ,  H03B5/12

Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

公开(公告)号：US09680553B1

公开(公告)日：2017-06-13

申请号：US14959794

申请日：2015-12-04

Applicant: Infineon Technologies AG

Inventor： Marc Tiebout ,  Andrew Stonehouse ,  Michele Caruso ,  Angus McLachlan ,  Alan Harvey ,  William MacIsaac ,  Johann Wuertele

IPC: H04L27/00 ,  H03C3/00 ,  H04B7/06 ,  H04B7/0408

CPC classification number: H01Q3/2682 ,  H01Q3/36 ,  H04B7/02 ,  H04B7/04 ,  H04B7/0408 ,  H04B7/0413 ,  H04B7/0617 ,  H04B7/0667 ,  H04B7/0671 ,  H04B7/084 ,  H04B7/086 ,  H04B7/0897

Abstract: In accordance with an embodiment a beamforming circuit having a radio frequency (RF) front end and a plurality of beamforming delay circuits coupled to the RF front end. Each of the plurality of beamforming delay circuits includes a common delay circuit and a plurality of individual delay circuits coupled to the common delay circuit. Each of the individual delay circuits are configured to be coupled to an antenna element of a beamforming array.

公开(公告)号：US20210036710A1

公开(公告)日：2021-02-04

申请号：US17073181

申请日：2020-10-16

Applicant: Infineon Technologies AG ,  Politecnico Di Milano

Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

IPC: H03L7/24 ,  H03B5/12 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

公开(公告)号：US20200169333A1

公开(公告)日：2020-05-28

申请号：US16683488

申请日：2019-11-14

Applicant: Infineon Technologies AG

Inventor： Marc Tiebout ,  Michele Caruso ,  Daniele Dal Maistro ,  Carlos Rubino

IPC: H04B17/13 ,  H04B17/19 ,  H04B1/04 ,  H03F1/32 ,  H03F3/21 ,  G01R29/26

Abstract: A circuit includes an amplifier and pre-distortion circuit. The amplifier amplifies a modulated signal. The signal pre-distortion circuit performs a feed-forward pre-distortion of the modulated signal in a signal path in which the amplifier resides. The signal pre-distortion circuit includes: i) an envelope detector configured operative to provide an envelope information describing an envelope of the modulated signal; and ii) a built-in test circuit that determines distortion information describing a distortion in the signal path caused by amplitude variations. The signal pre-distortion circuit performs the feed-forward pre-distortion of the modulated signal on the basis of the distortion information.

公开(公告)号：US20180241406A1

公开(公告)日：2018-08-23

申请号：US15438438

申请日：2017-02-21

Applicant: Infineon Technologies AG ,  Politecnico Di Milano

Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

IPC: H03L7/24 ,  H03L7/099 ,  H03B5/12

CPC classification number: H03L7/24 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B2201/0208 ,  H03L7/0991

Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

公开(公告)号：US20180175947A1

公开(公告)日：2018-06-21

申请号：US15825785

申请日：2017-11-29

Applicant: Infineon Technologies AG

Inventor： Marc Tiebout ,  Michele Caruso ,  Daniele Dal Maistro ,  Peter Thurner

IPC: H04B17/12 ,  H03L7/093 ,  H03L7/089 ,  H03L7/183 ,  H03G3/20 ,  H01Q3/36 ,  H01Q3/28 ,  H01Q3/26 ,  H04B17/13

CPC classification number: H04B17/12 ,  H01Q3/267 ,  H01Q3/28 ,  H01Q3/36 ,  H03G3/20 ,  H03G3/3036 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/183 ,  H03L7/22 ,  H04B17/13

Abstract: According to an embodiment, a radio frequency device includes a phase locked loop circuit, and an automatic gain control circuit, where an output of an automatic gain control circuit is coupled to a reference signal input of the phase locked loop circuit.