公开(公告)号：US11862582B2

公开(公告)日：2024-01-02

申请号：US17502084

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Bemmerl ,  Martin Gruber ,  Martin Richard Niessner

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/564 ,  H01L21/481 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49541 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.

公开(公告)号：US20200373228A1

公开(公告)日：2020-11-26

申请号：US16422163

申请日：2019-05-24

Applicant: Infineon Technologies AG

Inventor： Ke Yan Tean ,  Thomas Bemmerl ,  Thai Kee Gan ,  Azlina Kassim

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.

公开(公告)号：US20190189542A1

公开(公告)日：2019-06-20

申请号：US16219415

申请日：2018-12-13

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Kuok Wai Chan ,  Christoph Liebl ,  Bun Kian Tay ,  Wee Boon Tay ,  Wae Chet Yong

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49548 ,  H01L24/49

Abstract: A leadless package includes an at least partially electrically conductive carrier having a mounting section and a lead section, an electronic chip mounted on the mounting section, and an encapsulant at least partially encapsulating the electronic chip and partially encapsulating the carrier so that at least part of an interior sidewall of the lead section not forming part of an exterior sidewall of the package is exposed.

公开(公告)号：US20180338379A1

公开(公告)日：2018-11-22

申请号：US15982778

申请日：2018-05-17

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Joachim Mahler

IPC: H05K3/32 ,  B22F7/06 ,  H05K7/02

Abstract: An electronic device includes a component, an electronic component, and a joining material arranged between a surface of the component and a surface of the electronic component. Spacer elements are embedded in the joining material. Interconnects are arranged between the spacer elements and the surface of the component, and between the spacer elements and the surface of the electronic component.

公开(公告)号：US20190333874A1

公开(公告)日：2019-10-31

申请号：US16382866

申请日：2019-04-12

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.

公开(公告)号：US20250022780A1

公开(公告)日：2025-01-16

申请号：US18768582

申请日：2024-07-10

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device includes an encapsulation material at least partially encapsulating a semiconductor component of the semiconductor device. The semiconductor device further includes a lead protruding out of the encapsulation material and extending along a longitudinal axis, the lead comprising a twisted section along which the lead is twisted around the longitudinal axis. The twisted section of the lead is encapsulated in the encapsulation material, or the twisted section of the lead is external to the encapsulation material and provides an increased clearance distance between a residual dambar portion of the lead and an adjacent lead.

公开(公告)号：US11869830B2

公开(公告)日：2024-01-09

申请号：US16678000

申请日：2019-11-08

Applicant: Infineon Technologies AG

Inventor： Michael Stadler ,  Thomas Bemmerl

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49517 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/83 ,  H01L2224/83815

Abstract: A clip, a semiconductor package, and a method are disclosed. In one example the clip includes a die attach portion having a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and including a curved transition from an inner wall of the at least one through-hole to the first main face.

公开(公告)号：US10950509B2

公开(公告)日：2021-03-16

申请号：US16399603

申请日：2019-04-30

Applicant: Infineon Technologies AG

Inventor： Rainald Sander ,  Thomas Bemmerl ,  Steffen Thiele

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/66 ,  H01L23/495 ,  H01L21/48

Abstract: A semiconductor device includes a first chip pad, a power semiconductor chip arranged on the first chip pad and including at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.

公开(公告)号：US20190304858A1

公开(公告)日：2019-10-03

申请号：US16365837

申请日：2019-03-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Ralf Otremba ,  Thomas Bemmerl ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Meyer ,  Xaver Schloegel

IPC: H01L23/053 ,  H01L23/40 ,  H01L23/00 ,  H01L23/08

Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

公开(公告)号：US09484278B2

公开(公告)日：2016-11-01

申请号：US14091545

申请日：2013-11-27

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package includes a housing having a bottom surface and an upper surface and a solder pad arranged in the bottom surface of the housing. The solder pad includes a solderable through hole. The housing includes an opening extending from the through hole to the upper surface of the housing.

Abstract translation: 半导体封装包括具有底表面和上表面的壳体和布置在壳体的底表面中的焊盘。 焊盘包括可焊接通孔。 壳体包括从通孔延伸到壳体的上表面的开口。