公开(公告)号：US20170372952A1

公开(公告)日：2017-12-28

申请号：US15192146

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L21/288 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.

公开(公告)号：US20170069554A1

公开(公告)日：2017-03-09

申请号：US15352392

申请日：2016-11-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/66 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

Abstract translation: 一种形成电子器件的方法包括在工件中形成第一开口和第二开口。 第一个开口比第二个开口更深。 该方法还包括在第一开口内形成填充材料以形成通孔的一部分，并在第二开口内形成填充材料。

公开(公告)号：US20150364402A1

公开(公告)日：2015-12-17

申请号：US14834846

申请日：2015-08-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L23/48 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

Abstract translation: 根据本发明的实施例，一种形成电子装置的方法包括在工件中形成第一开口和第二开口。 第一个开口比第二个开口更深。 该方法还包括在第一开口内形成填充材料以形成通孔的一部分，并在第二开口内形成填充材料。

公开(公告)号：US09875933B2

公开(公告)日：2018-01-23

申请号：US15192146

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.

公开(公告)号：US09530720B2

公开(公告)日：2016-12-27

申请号：US14834846

申请日：2015-08-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/00 ,  H01L23/48 ,  H01L21/66 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

公开(公告)号：US10720359B2

公开(公告)日：2020-07-21

申请号：US15856742

申请日：2017-12-28

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/288

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.

公开(公告)号：US10014230B2

公开(公告)日：2018-07-03

申请号：US15352392

申请日：2016-11-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

公开(公告)号：US20180138086A1

公开(公告)日：2018-05-17

申请号：US15856742

申请日：2017-12-28

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/288 ,  H01L23/48

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.