-
公开(公告)号：US20220059347A1
公开(公告)日：2022-02-24
申请号：US16999308
申请日：2020-08-21
发明人： Ravi Keshav Joshi , Andreas Behrendt , Richard Gaisberger , Anita Satz , Johanna Schlaminger , Johann Schmid , Mario Stanovnik , Juergen Steinbrenner
IPC分类号： H01L21/02 , H01L21/768 , H01L21/3213 , H01L21/306 , H01L23/528
摘要： Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.
-
公开(公告)号：US20220285149A1
公开(公告)日：2022-09-08
申请号：US17825043
申请日：2022-05-26
发明人： Ravi Keshav Joshi , Andreas Behrendt , Richard Gaisberger , Anita Satz , Johanna Schlaminger , Johann Schmid , Mario Stanovnik , Juergen Steinbrenner
IPC分类号： H01L21/02 , H01L21/768 , H01L23/528 , H01L21/306 , H01L21/3213
摘要： Described herein are a method and a power semiconductor device produced by the method. The power semiconductor device includes: transistor device structures formed in a semiconductor substrate; a structured metallization layer above the semiconductor substrate; a first passivation over the structured metallization layer; a second passivation on the first passivation; an opening in the first passivation and the second passivation such that a first part of the structured metallization layer has a contact region uncovered by the first passivation and the second passivation and a peripheral region laterally surrounding the contact region and covered by the first passivation and the second passivation; a plating that covers the contact region but not the peripheral region of the first part of the structured metallization layer; and a protective layer separating the peripheral region of the first part of the structured metallization layer from the first passivation.
-
3.发明公开公开(公告)号：US20240318320A1
公开(公告)日：2024-09-26
申请号：US18731567
申请日：2024-06-03
发明人： Saurabh Roy , Matteo Dainese , Michael Ehmann , Hiroshi Narahashi , Johanna Schlaminger , Katharina Teichmann , Sigrid Wabnig
IPC分类号： C23F1/44 , H01L21/3213
CPC分类号： C23F1/44 , H01L21/32134
摘要： A semiconductor device includes a semiconductor substrate, a TiW layer arranged on the semiconductor substrate a Ti layer arranged on the TiW layer, a Ni alloy layer arranged on the Ti layer, and an Ag layer arranged on the Ni alloy layer, wherein the Ag layer and the Ni alloy layer comprise side faces fabricated by at least one wet etching process, and wherein the Ti layer and the TiW layer comprise side faces fabricated by a dry etching process.
-
公开(公告)号：US12018387B2
公开(公告)日：2024-06-25
申请号：US17582656
申请日：2022-01-24
发明人： Saurabh Roy , Matteo Dainese , Michael Ehmann , Hiroshi Narahashi , Johanna Schlaminger , Katharina Teichmann , Sigrid Wabnig
IPC分类号： C23F1/44 , H01L21/3213
CPC分类号： C23F1/44 , H01L21/32134
摘要： A method for fabricating a semiconductor device comprises depositing a TiW layer on a semiconductor substrate, depositing a Ti layer on the TiW layer, depositing a Ni alloy layer on the Ti layer, depositing an Ag layer on the Ni alloy layer, at least partially covering the Ag layer with photoresist, wet etching the Ag layer and the Ni alloy layer, and dry etching the Ti layer and the TiW layer.
-
公开(公告)号：US20220235470A1
公开(公告)日：2022-07-28
申请号：US17582656
申请日：2022-01-24
发明人： Saurabh Roy , Matteo Dainese , Michael Ehmann , Hiroshi Narahashi , Johanna Schlaminger , Katharina Teichmann , Sigrid Wabnig
IPC分类号： C23F1/44 , H01L21/3213
摘要： A method for fabricating a semiconductor device comprises depositing a TiW layer on a semiconductor substrate, depositing a Ti layer on the TiW layer, depositing a Ni alloy layer on the Ti layer, depositing an Ag layer on the Ni alloy layer, at least partially covering the Ag layer with photoresist, wet etching the Ag layer and the Ni alloy layer, and dry etching the Ti layer and the TiW layer.
-
公开(公告)号：US11387095B2
公开(公告)日：2022-07-12
申请号：US16999308
申请日：2020-08-21
发明人： Ravi Keshav Joshi , Andreas Behrendt , Richard Gaisberger , Anita Satz , Johanna Schlaminger , Johann Schmid , Mario Stanovnik , Juergen Steinbrenner
IPC分类号： H01L21/02 , H01L21/768 , H01L23/528 , H01L21/306 , H01L21/3213
摘要： Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.018 秒)
