公开(公告)号：US20170110331A1

公开(公告)日：2017-04-20

申请号：US15293533

申请日：2016-10-14

申请人： Infineon Technologies Austria AG

发明人： Ravi Keshav Joshi ,  Johannes Baumgartl ,  Georg Ehrentraut ,  Petra Fischer ,  Richard Gaisberger ,  Christoph Gruber ,  Martin Poelzl ,  Juergen Steinbrenner

IPC分类号： H01L21/308 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3063 ,  H01L29/739

CPC分类号： H01L21/3088 ,  H01L21/3063 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7813

摘要： A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate. A second layer of the layer stack is less etched or non-etched compared to the selective etching of the first layer of the layer stack, such that the first layer of the layer stack is laterally etched back between the semiconductor substrate and the second layer of the layer stack. The method further includes growing semiconductor material on regions of the surface of the semiconductor substrate exposed after the selective etching process.

公开(公告)号：US20170011927A1

公开(公告)日：2017-01-12

申请号：US15273589

申请日：2016-09-22

申请人： Infineon Technologies Austria AG

发明人： Juergen Steinbrenner ,  Markus Kahn ,  Helmut Schoenherr ,  Ravi Joshi ,  Heimo Hofer ,  Martin Poelzl ,  Harald Huetter

IPC分类号： H01L21/28 ,  H01L29/06 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L21/28185 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76801 ,  H01L21/76828 ,  H01L23/5329 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.

摘要翻译： 沉积绝缘层的方法包括通过以第一流速使用硅源和以第二流量的掺杂剂源沉积硅酸盐玻璃层来在特征的侧壁上进行初次沉积。 掺杂剂源的流量与硅源的流量的比率是第一比率。 该方法还包括通过增加硅源相对于掺杂源的流动的流动来在特征的侧壁上进行二次沉积。 掺杂剂源的流量与硅源的流量的比率是低于第一比率的第二比例，并且在执行二次沉积之后停止硅源的流动。 停止流动后进行回流处理。 在回流处理之后，特征的侧壁上的硅酸盐玻璃层的厚度变化在1％至20％之间。

公开(公告)号：US11387095B2

公开(公告)日：2022-07-12

申请号：US16999308

申请日：2020-08-21

申请人： Infineon Technologies Austria AG

发明人： Ravi Keshav Joshi ,  Andreas Behrendt ,  Richard Gaisberger ,  Anita Satz ,  Johanna Schlaminger ,  Johann Schmid ,  Mario Stanovnik ,  Juergen Steinbrenner

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L21/306 ,  H01L21/3213

摘要： Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

公开(公告)号：US20180182629A1

公开(公告)日：2018-06-28

申请号：US15850041

申请日：2017-12-21

申请人： Infineon Technologies Austria AG

发明人： Wolfgang Jantscher ,  Alexander Binter ,  Oliver Blank ,  Petra Fischer ,  Ravi Keshav Joshi ,  Kurt Pekoll ,  Manfred Pippan ,  Andreas Riegler ,  Werner Schustereder ,  Juergen Steinbrenner ,  Waqas Mumtaz Syed

IPC分类号： H01L21/266 ,  H01L21/324 ,  H01L21/768 ,  H01L21/308 ,  H01L29/66

CPC分类号： H01L21/266 ,  H01L21/308 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76847 ,  H01L21/76864 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/66712 ,  H01L29/7396 ,  H01L2221/1063

摘要： Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.

公开(公告)号：US09768273B2

公开(公告)日：2017-09-19

申请号：US15187232

申请日：2016-06-20

申请人： Infineon Technologies Austria AG

发明人： Ravi Joshi ,  Johannes Baumgartl ,  Martin Poelzl ,  Matthias Kuenle ,  Juergen Steinbrenner ,  Andreas Haghofer ,  Christoph Gruber ,  Georg Ehrentraut

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/423 ,  H01L29/78 ,  H01L21/308

CPC分类号： H01L29/66613 ,  H01L21/02233 ,  H01L21/02647 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7827

摘要： In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.

公开(公告)号：US20220285149A1

公开(公告)日：2022-09-08

申请号：US17825043

申请日：2022-05-26

申请人： Infineon Technologies Austria AG

发明人： Ravi Keshav Joshi ,  Andreas Behrendt ,  Richard Gaisberger ,  Anita Satz ,  Johanna Schlaminger ,  Johann Schmid ,  Mario Stanovnik ,  Juergen Steinbrenner

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L21/306 ,  H01L21/3213

摘要： Described herein are a method and a power semiconductor device produced by the method. The power semiconductor device includes: transistor device structures formed in a semiconductor substrate; a structured metallization layer above the semiconductor substrate; a first passivation over the structured metallization layer; a second passivation on the first passivation; an opening in the first passivation and the second passivation such that a first part of the structured metallization layer has a contact region uncovered by the first passivation and the second passivation and a peripheral region laterally surrounding the contact region and covered by the first passivation and the second passivation; a plating that covers the contact region but not the peripheral region of the first part of the structured metallization layer; and a protective layer separating the peripheral region of the first part of the structured metallization layer from the first passivation.

公开(公告)号：US10347491B2

公开(公告)日：2019-07-09

申请号：US15850041

申请日：2017-12-21

申请人： Infineon Technologies Austria AG

发明人： Wolfgang Jantscher ,  Alexander Binter ,  Oliver Blank ,  Petra Fischer ,  Ravi Keshav Joshi ,  Kurt Pekoll ,  Manfred Pippan ,  Andreas Riegler ,  Werner Schustereder ,  Juergen Steinbrenner ,  Waqas Mumtaz Syed

IPC分类号： H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L21/308 ,  H01L21/768 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06

摘要： Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.

公开(公告)号：US20220059347A1

公开(公告)日：2022-02-24

申请号：US16999308

申请日：2020-08-21

申请人： Infineon Technologies Austria AG

发明人： Ravi Keshav Joshi ,  Andreas Behrendt ,  Richard Gaisberger ,  Anita Satz ,  Johanna Schlaminger ,  Johann Schmid ,  Mario Stanovnik ,  Juergen Steinbrenner

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/306 ,  H01L23/528

摘要： Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

公开(公告)号：US20170005091A1

公开(公告)日：2017-01-05

申请号：US15196999

申请日：2016-06-29

申请人： Infineon Technologies Austria AG

发明人： Ravi Keshav Joshi ,  Johannes Baumgartl ,  Christoph Gruber ,  Andreas Haghofer ,  Martin Poelzl ,  Juergen Steinbrenner

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/41791 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor laminar structure arranged on a semiconductor substrate. The semiconductor laminar structure includes a first doping region of a field effect transistor structure and at least a part of a body region of the field effect transistor structure. The body region has a first conductivity type and the first doping region has a second conductivity type. The semiconductor device further includes an electrically conductive contact structure providing an electrical contact to the first doping region of the field effect transistor structure and to the body region of the field effect transistor structure at one or more sidewalls of the semiconductor laminar structure.

摘要翻译： 半导体器件包括布置在半导体衬底上的半导体层状结构。 半导体层状结构包括场效应晶体管结构的第一掺杂区域和场效应晶体管结构的体区的至少一部分。 体区具有第一导电类型，第一掺杂区具有第二导电类型。 半导体器件还包括导电接触结构，其提供与场效应晶体管结构的第一掺杂区域的电接触以及半导体层状结构的一个或多个侧壁处的场效应晶体管结构的体区。

公开(公告)号：US20160308028A1

公开(公告)日：2016-10-20

申请号：US15187232

申请日：2016-06-20

申请人： Infineon Technologies Austria AG

发明人： Ravi Joshi ,  Johannes Baumgartl ,  Martin Poelzl ,  Matthias Kuenle ,  Juergen Steinbrenner ,  Andreas Haghofer ,  Christoph Gruber ,  Georg Ehrentraut

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L29/66613 ,  H01L21/02233 ,  H01L21/02647 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7827

摘要： In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.

摘要翻译： 一方面，在半导体材料中形成沟槽的方法包括在半导体衬底上形成第一电介质层。 第一介电层包括第一开口。 通过外延横向过度生长工艺在半导体衬底上生长外延层。 第一开口由外延层填充，并且外延层生长到第一介电层的相邻部分上，使得第一介电层的一部分未被外延层覆盖，并且在外延层的相对侧壁之间形成间隙 由外延层未覆盖的第一电介质层的一部分。 该间隙限定外延层中延伸到第一介电层的第一沟槽。