利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.015 秒)

    Efficient buffer utilization for network data units
    1.
    发明授权
    Efficient buffer utilization for network data units 有权

    公开(公告)号：US11949601B1

    公开(公告)日：2024-04-02

    申请号：US17942676

    申请日：2022-09-12

    申请人： Innovium, Inc.

    发明人： Ajit Kumar Jain ,  Mohammad Kamel Issa ,  Avinash Gyanendra Mani ,  Ashwin Alapati

    IPC分类号： H04L47/785 ,  H04L45/74 ,  H04L47/30 ,  H04L47/41

    CPC分类号： H04L47/786 ,  H04L45/74 ,  H04L47/30 ,  H04L47/41

    摘要： Approaches, techniques, and mechanisms are disclosed for efficiently buffering data units within a network device. A traffic manager or other network device component receives Transport Data Units (“TDUs”), which are sub-portions of Protocol Data Units (“PDUs”). Rather than buffer an entire TDU together, the component divides the TDU into multiple Storage Data Units (“SDUs”) that can fit in SDU buffer entries within physical memory banks. A TDU-to-SDU Mapping (“TSM”) memory stores TSM lists that indicate which SDU entries store SDUs for a given TDU. Physical memory banks in which the SDUs are stored may be grouped together into logical SDU banks that are accessed together as if a single bank. The TSM memory may include a number of distinct TSM banks, with each logical SDU bank having a corresponding TSM bank. Techniques for maintaining inter-packet and intra-packet linking data compatible with such buffers are also disclosed.

    SYSTEM AND METHOD FOR ENABLING HIGH READ RATES TO DATA ELEMENT LISTS
    2.
    发明申请
    SYSTEM AND METHOD FOR ENABLING HIGH READ RATES TO DATA ELEMENT LISTS 审中-公开

    公开(公告)号：US20180081577A1

    公开(公告)日：2018-03-22

    申请号：US15815854

    申请日：2017-11-17

    申请人： Innovium, Inc.

    发明人： William Brad Matthews ,  Bruce H. Kwan ,  Mohammad K. Issa ,  Neil Barrett ,  Avinash Gyanendra Mani

    IPC分类号： G06F3/06 ,  G06F12/06

    摘要： A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a link memory that is configured to maintain one or more pointers to interconnect the one or more data elements stored in the main memory. The memory system also includes a free-entry manager that is configured to generate an available bank set including one or more locations in the link memory. In addition, the memory system includes a context manager that is configured to maintain metadata for a list of the one or more data elements.

    Network chip yield improvement architectures and techniques
    8.
    发明授权
    Network chip yield improvement architectures and techniques 有权

    公开(公告)号：US11481350B1

    公开(公告)日：2022-10-25

    申请号：US16940003

    申请日：2020-07-27

    申请人： Innovium, Inc.

    发明人： Srinivas Gangam ,  Ajit Kumar Jain ,  Anurag Kumar Jain ,  Avinash Gyanendra Mani ,  Mohammad Kamel Issa

    IPC分类号： G06F13/40 ,  H03M9/00 ,  G06F13/42

    摘要： Network chip utility is improved using multi-core architectures with auxiliary wiring between cores to permit cores to utilize components from otherwise inactive cores. The architectures permit, among other advantages, the re-purposing of functional components that reside in defective or otherwise non-functional cores. For instance, a four-core network chip with certain defects in three or even four cores could still, through operation of the techniques described herein, be utilized in a two or even three-core capacity. In an embodiment, the auxiliary wiring may be used to redirect data from a Serializer/Deserializer (“SerDes”) block of a first core to packet-switching logic on a second core, and vice-versa. In an embodiment, the auxiliary wiring may be utilized to circumvent defective components in the packet-switching logic itself. In an embodiment, a core may utilize buffer memories, forwarding tables, or other resources from other cores instead of or in addition to its own.

    Efficient buffer utilization for network data units
    9.
    发明授权
    Efficient buffer utilization for network data units 有权

    公开(公告)号：US11470016B1

    公开(公告)日：2022-10-11

    申请号：US16924340

    申请日：2020-07-09

    申请人： Innovium, Inc.

    发明人： Ajit Kumar Jain ,  Mohammad Kamel Issa ,  Avinash Gyanendra Mani ,  Ashwin Alapati

    IPC分类号： H04L47/785 ,  H04L45/74 ,  H04L47/30 ,  H04L47/41

    摘要： Approaches, techniques, and mechanisms are disclosed for efficiently buffering data units within a network device. A traffic manager or other network device component receives Transport Data Units (“TDUs”), which are sub-portions of Protocol Data Units (“PDUs”). Rather than buffer an entire TDU together, the component divides the TDU into multiple Storage Data Units (“SDUs”) that can fit in SDU buffer entries within physical memory banks. A TDU-to-SDU Mapping (“TSM”) memory stores TSM lists that indicate which SDU entries store SDUs for a given TDU. Physical memory banks in which the SDUs are stored may be grouped together into logical SDU banks that are accessed together as if a single bank. The TSM memory may include a number of distinct TSM banks, with each logical SDU bank having a corresponding TSM bank. Techniques for maintaining inter-packet and intra-packet linking data compatible with such buffers are also disclosed.

    High-throughput multi-node integrated circuits
    10.
    发明授权
    High-throughput multi-node integrated circuits 有权

    公开(公告)号：US11265268B1

    公开(公告)日：2022-03-01

    申请号：US16780214

    申请日：2020-02-03

    申请人： Innovium, Inc.

    发明人： Ajit K. Jain ,  Avinash Gyanendra Mani ,  Mohammad Kamel Issa

    IPC分类号： H04L12/935 ,  H04L49/00 ,  H04L1/00

    摘要： The technology described in this document can be embodied in an integrated circuit device comprises a first data processing unit comprising one or more input ports for receiving incoming data, one or more inter-unit data links that couple the first data processing unit to one or more other data processing units, a first ingress management module connected to the one or more inter-unit data links, the first ingress management module configured to store the incoming data, and forward the stored data to the one or more inter-unit data links as multiple data packets, and a first ingress processing module. The integrated circuit device also comprises a second data processing unit comprising one or more output ports for transmitting outgoing data, and a second ingress management module connected to the one or more inter-unit data links.