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    Clock distribution systems for low power applications
    1.
    发明授权
    Clock distribution systems for low power applications 有权
    低功率应用的时钟分配系统

    公开(公告)号：US08854086B1

    公开(公告)日：2014-10-07

    申请号：US13795828

    申请日：2013-03-12

    Applicant: Integrated Device Technology, Inc.

    Inventor： Jagdeep Bal ,  Cheng Wen Hsiao

    IPC: G06F1/08 ,  H03K3/012

    CPC classification number: H03K3/012 ,  G06F1/08 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/3278 ,  Y02D10/126 ,  Y02D10/157

    Abstract: Integrated circuit devices include first and second periodic signal generators and a power down detection circuit. The first periodic signal generator is configured to generate at least a first periodic signal having a first frequency at an output thereof and the second periodic signal generator is configured to generate a second periodic signal having a second frequency less than the first frequency at an output thereof. The power down detection circuit is configured to selectively provide one or the other of the first and second periodic signals to an output terminal of the integrated circuit device, in response to monitoring a status of a signal received at an input terminal of the integrated circuit device. This received signal reflects a power down status of an external device that receives the selected one of the first and second periodic signals.

    Abstract translation: 集成电路装置包括第一和第二周期信号发生器和断电检测电路。 第一周期信号发生器被配置为在其输出处产生具有第一频率的至少第一周期性信号，并且第二周期信号发生器被配置为在其输出处产生具有小于第一频率的第二频率的第二周期信号 。 断电检测电路被配置为响应于监视在集成电路装置的输入端子处接收的信号的状态而选择性地将第一和第二周期信号中的一个或另一个提供给集成电路装置的输出端子 。 该接收到的信号反映了接收第一和第二周期信号中所选择的一个的外部设备的掉电状态。

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