公开(公告)号：US09490805B2

公开(公告)日：2016-11-08

申请号：US14475544

申请日：2014-09-02

申请人： Integrated Device Technology, Inc.

发明人： John Hsu

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/0005 ,  H03K19/00361 ,  H03K19/01855 ,  H03K19/018585

摘要： A programmable low power driver permits an output impedance of the driver to be programmed. Programmability permits the driver output impedance to match an impedance of a transmission line that is connected thereto. The low power driver includes a first driver output and a plurality of driver legs. The programmable low power driver is configured to electrically couple one or more driver legs of the plurality of driver legs to the first driver output to establish an output impedance for the driver.

摘要翻译： 可编程低功率驱动器允许对驱动器的输出阻抗进行编程。 可编程性允许驱动器输出阻抗匹配与其连接的传输线的阻抗。 低功率驱动器包括第一驱动器输出和多个驱动器脚。 可编程低功率驱动器被配置为将多个驱动器支路中的一个或多个驱动器支路电耦合到第一驱动器输出以建立用于驱动器的输出阻抗。

公开(公告)号：US20160065211A1

公开(公告)日：2016-03-03

申请号：US14475544

申请日：2014-09-02

申请人： Integrated Device Technology, Inc.

发明人： John Hsu

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K19/003

CPC分类号： H03K19/0005 ,  H03K19/00361 ,  H03K19/01855 ,  H03K19/018585

摘要： A low power programmable driver includes a first driver output, a first programmable driver leg and a second programmable driver leg. The first programmable driver leg has a pull-up half and a pull-down half. The pull-up half is electrically coupled between a supply voltage and the first driver output. The pull-up half is electrically coupled to receive a signal and a first control signal. The pull-down half is electrically coupled between an internal ground and the first driver output. The pull-down half is electrically coupled to receive an inversion of the signal and the first control signal. A second programmable driver leg has a pull-up half and a pull-down half. The pull-up half is electrically coupled between the supply voltage and the first driver output. The pull-up half is electrically coupled to receive the signal and a second control signal. The pull-down half is electrically coupled between the internal ground and the first driver output. The pull-down half is electrically coupled to receive the inversion of the signal and the second control signal. The first programmable driver leg contributes to a termination impedance of the driver when the first control signal is high and does not contribute to the termination impedance when the first control signal is low. The second programmable driver leg contributes to the termination impedance of the driver when the second control signal is high and does not contribute to the termination impedance when the second control signal is low.

摘要翻译： 低功率可编程驱动器包括第一驱动器输出，第一可编程驱动器支路和第二可编程驱动器支路。 第一个可编程驱动器脚有一个上拉一半和一个下拉一半。 上拉一半电耦合在电源电压和第一驱动器输出之间。 上拉一半电耦合以接收信号和第一控制信号。 下拉一半电连接在内部接地和第一驱动器输出之间。 下拉一半电耦合以接收信号和第一控制信号的反相。 第二可编程驱动器支脚具有上拉一半和下拉一半。 上拉一半电耦合在电源电压和第一驱动器输出之间。 上拉一半电耦合以接收信号和第二控制信号。 下拉一半电连接在内部接地和第一个驱动器输出之间。 下拉一半电耦合以接收信号的反转和第二控制信号。 当第一控制信号为高电平并且当第一控制信号为低时，第一可编程驱动器引脚有助于驱动器的终端阻抗。 当第二控制信号为高时，第二可编程驱动器支路有助于驱动器的端接阻抗，并且当第二控制信号为低时不对终端阻抗有贡献。

公开(公告)号：US09495285B2

公开(公告)日：2016-11-15

申请号：US14488262

申请日：2014-09-16

申请人： Integrated Device Technology, Inc.

发明人： John Hsu ,  Hui Li

IPC分类号： G06F1/00 ,  G06F12/02 ,  G06F12/06 ,  G11C7/20 ,  G11C11/413 ,  G11C11/00

CPC分类号： G06F12/0238 ,  G06F12/0638 ,  G06F2212/202 ,  G11C7/20 ,  G11C11/005 ,  G11C11/413

摘要： The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.

摘要翻译： 本发明提供了一种方法和可编程定时装置，其包括用于产生至少一个定时信号的定时装置电路，耦合到定时装置电路的静态随机存取存储器（SRAM），具有第一 存储其中的定时设备配置，用于存储第二定时设备配置和选择逻辑的一次性可编程非易失性存储器（OTP NVM）。 选择逻辑包括耦合到SRAM的输出，耦合到ROM的第一输入和耦合到OTP NVM的第二输入。 选择逻辑可操作以接收指示是否要从ROM或OTP NVM加载SRAM的输入，并且可操作以基于输入从OTP NVM加载来自ROM的第一定时设备配置或第二定时设备配置 。

公开(公告)号：US20160077958A1

公开(公告)日：2016-03-17

申请号：US14488262

申请日：2014-09-16

申请人： Integrated Device Technology, Inc.

发明人： John Hsu ,  Hui Li

IPC分类号： G06F12/02

CPC分类号： G06F12/0238 ,  G06F12/0638 ,  G06F2212/202 ,  G11C7/20 ,  G11C11/005 ,  G11C11/413

摘要： The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.

摘要翻译： 本发明提供了一种方法和可编程定时装置，其包括用于产生至少一个定时信号的定时装置电路，耦合到定时装置电路的静态随机存取存储器（SRAM），具有第一 存储在其中的定时设备配置，用于存储第二定时设备配置和选择逻辑的一次性可编程非易失性存储器（OTP NVM）。 选择逻辑包括耦合到SRAM的输出，耦合到ROM的第一输入和耦合到OTP NVM的第二输入。 选择逻辑可操作以接收指示是否要从ROM或OTP NVM加载SRAM的输入，并且可操作以基于输入从OTP NVM加载来自ROM的第一定时设备配置或第二定时设备配置 。

公开(公告)号：US09847869B1

公开(公告)日：2017-12-19

申请号：US15210204

申请日：2016-07-14

申请人： Integrated Device Technology, Inc.

发明人： Chung-Yu Wu ,  Wei-Ching Chan ,  John Hsu ,  Cheng Wen Hsiao

IPC分类号： H03D3/24 ,  H04L7/033 ,  H04L12/70

CPC分类号： H03L7/104 ,  H03L7/183 ,  H04L2012/5681

摘要： A frequency synthesizer with microcode control that allows one or more programmable circuits of a frequency synthesizer system to be programmed using a plurality of microcode instructions. A method includes, setting a frequency synthesizer system to operate in a microcode mode, programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions and executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system.

公开(公告)号：US09419588B1

公开(公告)日：2016-08-16

申请号：US14628215

申请日：2015-02-21

申请人： Integrated Device Technology, Inc.

发明人： John Hsu

IPC分类号： H03K3/01 ,  H03K3/012

CPC分类号： H04L25/0278 ,  H03K3/012 ,  H03K19/0005 ,  H03K19/00384 ,  H03K19/018571

摘要： An output driver is provided that adapts an output impedance of the output driver to the voltage level of a power supply, thereby providing a constant output impedance over a range of different operating voltages. The output driver includes a plurality of individual driver circuits, each one of the plurality of individual driver circuits configured to provide a plurality of predetermined output impedances in response to a plurality of power supply voltage level inputs and a decoder. The decoder of the output driver is configured for receiving a digital codeword representative of a voltage level of a power supply coupled to the output driver and for decoding the digital codeword to activate one or more of the individual driver circuits to provide a constant output impedance from the output driver in response to the voltage level of the power supply coupled to the output driver, wherein the constant output impedance is a combination of the predetermined output impedances of the activated individual driver circuits.

摘要翻译： 提供了一种输出驱动器，其将输出驱动器的输出阻抗调整到电源的电压电平，从而在不同工作电压范围内提供恒定的输出阻抗。 输出驱动器包括多个单独的驱动器电路，多个单独驱动器电路中的每一个被配置为响应于多个电源电压电平输入和解码器而提供多个预定的输出阻抗。 输出驱动器的解码器被配置为用于接收代表耦合到输出驱动器的电源的电压电平的数字代码字，并且用于对数字代码字进行解码以激活单个驱动器电路中的一个或多个以提供恒定的输出阻抗 所述输出驱动器响应于耦合到所述输出驱动器的电源的电压电平，其中所述恒定输出阻抗是所激活的各个驱动器电路的预定输出阻抗的组合。

公开(公告)号：US09407268B1

公开(公告)日：2016-08-02

申请号：US14700034

申请日：2015-04-29

申请人： Integrated Device Technology, Inc.

发明人： John Hsu

IPC分类号： H03K3/00 ,  H03K19/0185

CPC分类号： H03K19/018528

摘要： An low voltage differential signaling (LVDS) driver is provide having an output voltage amplitude regulator for regulating an output voltage amplitude of the LVDS driver by receiving a differential output signal from a switched-polarity current generator of the LVDS driver at an output voltage amplitude regulator of the LVDS driver, detecting an output voltage amplitude of the differential output signal, comparing the output voltage amplitude to a reference voltage at the output voltage amplitude regulator and regulating a steering current of the LVDS driver based upon the comparison between the output voltage amplitude and the reference voltage to regulate an amplitude of the differential output signal at one or more loads of the LVDS driver.

摘要翻译： 提供具有输出电压幅度调节器的低电压差分信号（LVDS）驱动器，用于通过在输出电压幅度调节器处接收来自LVDS驱动器的开关极性电流发生器的差分输出信号来调节LVDS驱动器的输出电压幅度 检测差分输出信号的输出电压幅度，将输出电压幅度与输出电压幅度调节器上的参考电压进行比较，并根据输出电压幅度和输出电压振幅之间的比较来调节LVDS驱动器的转向电流 参考电压以调节LVDS驱动器的一个或多个负载处的差分输出信号的幅度。

公开(公告)号：US09336896B1

公开(公告)日：2016-05-10

申请号：US14666226

申请日：2015-03-23

申请人： Integrated Device Technology, Inc.

发明人： John Hsu

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C17/16

摘要： An integrated circuit is provided that allows for the use of the same supply voltage pin to receive both a normal operating voltage for the integrated circuit (IC) and a one-time-programmable (OTP) memory program voltage sufficient to program an OTP memory located on the integrated circuit. In one embodiment, when an OTP programming voltage is received at a supply voltage pin of the IC, the OTP programming voltage is provided to the OTP memory of the integrated circuit and the OTP programming voltage is regulated to the normal operating voltage level prior to providing the voltage to the internal circuitry of the integrated circuit. As such, the present invention establishes a dual-purpose supply voltage pin, thereby eliminating the need for a separate OTP programming voltage pin on the integrated circuit.

摘要翻译： 提供一种集成电路，其允许使用相同的电源电压引脚来接收用于集成电路（IC）的正常工作电压和足以编程位于所述OTP存储器的一次可编程（OTP）存储器程序电压 在集成电路上。 在一个实施例中，当在IC的电源电压引脚处接收到OTP编程电压时，将OTP编程电压提供给集成电路的OTP存储器，并且OTP编程电压在提供之前被调节到正常工作电压电平 电压到集成电路的内部电路。 因此，本发明建立了一种双用途电源电压引脚，从而不需要集成电路上的单独的OTP编程电压引脚。