公开(公告)号：US11256639B2

公开(公告)日：2022-02-22

申请号：US15791182

申请日：2017-10-23

Applicant: Intel Corporation

Inventor： Rajaram Regupathy ,  Abdul R. Ismail

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/26 ,  G06F13/362 ,  H04L41/12 ,  H04L41/0893 ,  H04L41/0853 ,  H04L41/0806

Abstract: A method and a device to participate in a managed Universal Serial Bus (USB) ecosystem. The method including establishing a connection with a plurality of devices in the ecosystem as a many-to-many relationship between extended USB device policy managers, and coordinating power and data exchange within the plurality of devices the ecosystem including at least one device that is not directly connected.

公开(公告)号：US09558145B2

公开(公告)日：2017-01-31

申请号：US14991293

申请日：2016-01-08

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

IPC: H04B17/00 ,  G06F13/42 ,  G06F13/00 ,  G06F13/38 ,  G06F1/14

CPC classification number: G06F13/4282 ,  G06F1/14 ,  G06F13/00 ,  G06F13/385 ,  H04L43/0858 ,  H04L43/106

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的镜像弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，并确定传送 数据元素至少部分地基于计数器输出采样和当前计数器值来遍历接收器电路的等待时间。 描述和要求保护其他实施例。

公开(公告)号：US20160350247A1

公开(公告)日：2016-12-01

申请号：US14750603

申请日：2015-06-25

Applicant: INTEL CORPORATION

Inventor： John S. Howard ,  Karthi R. Vadivelu ,  Abdul R. Ismail

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/36 ,  G06F13/4063 ,  G06F13/4282

Abstract: Techniques for latency improvement are described herein. The techniques may include an apparatus having a receiver configured to receive transfers over a bus. The transfers include a periodic transfer at a predefined interval, wherein the periodic transfer is associated with a guaranteed bandwidth over the bus. The transfers may also include an asynchronous transfer at any time within the predefined interval. The apparatus may also include logic configured to implement a modified periodic transfer at an interval that is less than the predefined interval, and a modified asynchronous transfer comprising a priority status above the asynchronous transfer.

Abstract translation: 本文描述了用于等待时间改善的技术。 这些技术可以包括具有被配置为通过总线接收传输的接收机的设备。 传输包括以预定间隔的周期性传输，其中周期性传输与总线上的保证带宽相关联。 传输还可以在预定义的间隔内的任何时间包括异步传送。 该装置还可以包括被配置为以小于预定义间隔的间隔实现修改的周期性传输的逻辑，以及包括高于异步传输的优先级状态的修改的异步传输。

公开(公告)号：US09262347B2

公开(公告)日：2016-02-16

申请号：US14126926

申请日：2013-10-30

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

IPC: H04B17/00 ,  G06F13/00

CPC classification number: G06F13/4282 ,  G06F1/14 ,  G06F13/00 ,  G06F13/385 ,  H04L43/0858 ,  H04L43/106

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的镜像弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，并确定传送 数据元素至少部分地基于计数器输出采样和当前计数器值来遍历接收器电路的等待时间。 描述和要求保护其他实施例。

公开(公告)号：US11263165B2

公开(公告)日：2022-03-01

申请号：US15396573

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Karthi R. Vadivelu ,  Abdul R. Ismail ,  Nausheen Ansari

IPC: G06F13/42 ,  G06F13/40

Abstract: Apparatuses relating to periodic Universal Serial Bus (USB) transaction scheduling at fractional bus intervals are described. In one embodiment, an apparatus includes a receptacle to receive a plug of a first device and a second device; a transceiver circuit coupled to the receptacle; and a controller circuit to: switch between a first mode for a first class of data transfers and a second mode for a second class of data transfers, wherein the first class preempts the second class of data transfers, schedule a data transfer with the transceiver circuit for a first endpoint of the first device at a first service interval of a bus interval when in the first mode, and schedule a data transfer with the transceiver circuit for a second, different endpoint of the second device at a second service interval that is smaller than the first service interval when in the first mode.

公开(公告)号：US20190086994A1

公开(公告)日：2019-03-21

申请号：US15709111

申请日：2017-09-19

Applicant: Intel Corporation

Inventor： Rajaram Regupathy ,  Abdul R. Ismail

IPC: G06F1/32 ,  G06F13/38

Abstract: An first apparatus is provided which comprises: a first port coupled to a second port of a second apparatus; first one or more circuitries to monitor current of a power bus that is to supply power from the first port to the second port; and second one or more circuitries to: while the first port is to operate in a high-current mode of operation, determine that the current of the power bus is less than a threshold current; and cause the first port to enter a suspend mode of operation from the high-current mode of operation, in response to the current of the power bus being less than the threshold current.

公开(公告)号：US20190042523A1

公开(公告)日：2019-02-07

申请号：US16006682

申请日：2018-06-12

Applicant: Intel Corporation

Inventor： Abdul R. Ismail ,  Rajaram Regupathy

IPC: G06F13/42

Abstract: An apparatus is provided, where the apparatus includes a plurality of input/output (I/O) ports and a controller. A first port, a second port, and a third port are to be respectively coupled to a first device with a first class type, a second device with a second class type, and a third device with a third class type. The controller is to determine that individual ones of the first and second devices are to perform asynchronous transfer with the apparatus, and that the third device is to perform a transfer that is different from the asynchronous transfer. The controller is to allocate bandwidth to the first and second I/O ports, based at least in part on the first class type and the second class type. The controller is to ignore the third class type, while allocating bandwidth to the third I/O port.

公开(公告)号：US11169589B2

公开(公告)日：2021-11-09

申请号：US16235867

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Rajaram Regupathy ,  Abdul R. Ismail

IPC: G06F1/32 ,  G06F1/3234 ,  G06F13/42 ,  G06F1/3228 ,  G06F1/3296

Abstract: Embodiments are directed toward a universal serial bus (USB) controller including a USB Type-C port that couples to a USB Type-C link including high speed data lines and an alternate mode function line to carry low power commands related to an alternate mode function. In embodiments, the controller or a processor coupled to the controller monitors the line used by the alternate mode function for the low power commands and provides information about the low power commands to a device policy manager (DPM) to determine a power distribution policy for a plurality of devices coupled to the DPM. In embodiments, the power distribution policy supplements or replaces a low power policy of a device of using a USB-C/Power delivery policy and another device using an alternate mode low power policy. Other embodiments may be described and/or claimed.

公开(公告)号：US11074211B2

公开(公告)日：2021-07-27

申请号：US16006682

申请日：2018-06-12

Applicant: Intel Corporation

Inventor： Abdul R. Ismail ,  Rajaram Regupathy

IPC: G06F13/42 ,  G06F13/38

Abstract: An apparatus is provided, where the apparatus includes a plurality of input/output (I/O) ports and a controller. A first port, a second port, and a third port are to be respectively coupled to a first device with a first class type, a second device with a second class type, and a third device with a third class type. The controller is to determine that individual ones of the first and second devices are to perform asynchronous transfer with the apparatus, and that the third device is to perform a transfer that is different from the asynchronous transfer. The controller is to allocate bandwidth to the first and second I/O ports, based at least in part on the first class type and the second class type. The controller is to ignore the third class type, while allocating bandwidth to the third I/O port.

公开(公告)号：US20210117347A1

公开(公告)日：2021-04-22

申请号：US17134089

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Jaya L. Jeyaseelan ,  Barnes Cooper ,  Abdul R. Ismail

IPC: G06F13/16 ,  G06F1/3234 ,  G06T1/20

Abstract: Techniques for controlling input/output (I/O) power usage are disclosed. In the illustrative embodiment, a power policy engine of a compute device monitors power usage, I/O data transfer rates, and temperature and determines when there should be a change in an I/O power setting. The I/O data transfer requires that the data be handled properly, causing the compute device to expend power on the I/O data transfer. The power policy engine may instruct a device driver, such as a driver of an I/O device, to change a data transfer rate of the I/O device, reducing the power the compute device spends handling I/O.