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公开(公告)号：US20230039853A1
公开(公告)日：2023-02-09
申请号：US17968469
申请日：2022-10-18
Applicant: Intel Corporation
Inventor： Balaji Vembu , Brandon Fliflet , James Valerio , Michael Apodaca , Ben Ashbaugh , Hema Nalluri , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Abhishek R. Appu , Joydeep Ray , Travis Schluessler
Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.
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公开(公告)号：US11481864B2
公开(公告)日：2022-10-25
申请号：US17234039
申请日：2021-04-19
Applicant: Intel Corporation
Inventor： Balaji Vembu , Brandon Fliflet , James Valerio , Michael Apodaca , Ben Ashbaugh , Hema Nalluri , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Abhishek R. Appu , Joydeep Ray , Travis Schluessler
Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.
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公开(公告)号：US12164952B2
公开(公告)日：2024-12-10
申请号：US17358882
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , James Valerio , Joydeep Ray , Abhishek R. Appu , Alan Curtis , Prathamesh Raghunath Shinde , Brandon Fliflet , Ben J. Ashbaugh , John Wiegert
Abstract: An apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. The apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (TG) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (TG) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the TG, cause, by the thread of the TG having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the TG.
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公开(公告)号：US11288191B1
公开(公告)日：2022-03-29
申请号：US17132147
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Hema Chand Nalluri , Aditya Navale , Altug Koker , Brandon Fliflet , Jeffery S. Boles , James Valerio , Vasanth Ranganathan , Anirban Kundu , Pattabhiraman K
IPC: G06F12/0802
Abstract: An apparatus to facilitate memory flushing is disclosed. The apparatus comprises a cache memory, one or more processing resources, tracker hardware to dispatch workloads for execution at the processing resources and to monitor the workloads to track completion of the execution, range based flush (RBF) hardware to process RBF commands and generate a flush indication to flush data from the cache memory and a flush controller to receive the flush indication and perform a flush operation to discard data from the cache memory at an address range provided in the flush indication.
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公开(公告)号：US10796472B2
公开(公告)日：2020-10-06
申请号：US16024821
申请日：2018-06-30
Applicant: Intel Corporation
Inventor： Michael Apodaca , Ankur Shah , Ben Ashbaugh , Brandon Fliflet , Hema Nalluri , Pattabhiraman K , Peter Doyle , Joseph Koston , James Valerio , Murali Ramadoss , Altug Koker , Aditya Navale , Prasoonkumar Surti , Balaji Vembu
IPC: G06T15/00
Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.
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Patent Agency Ranking
公开(公告)号：US20230051227A1
公开(公告)日：2023-02-16
申请号：US17978426
申请日：2022-11-01
Applicant: Intel Corporation
Inventor： Michal Mrozek , Bartosz Dunajski , Ben Ashbaugh , Brandon Fliflet
Abstract: An apparatus to facilitate processing in a multi-tile device is disclosed. In one embodiment, the apparatus includes a graphics processor comprising a first semiconductor die including a first high-bandwidth memory (HBM) device, a second semiconductor die including a second HBM device, and a third semiconductor die coupled with the first semiconductor die and the second semiconductor die in a 2.5-dimensional (2.5D) arrangement. The third semiconductor die includes a graphics processing resource and a cache coupled with the graphics processing resource. The cache is configurable to cache data associated with memory accessed by the graphics processing resource and the graphics processing resource includes a general-purpose graphics processor core and a tensor core.
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公开(公告)号：US20210241418A1
公开(公告)日：2021-08-05
申请号：US17234039
申请日：2021-04-19
Applicant: Intel Corporation
Inventor： Balaji Vembu , Brandon Fliflet , James Valerio , Michael Apodaca , Ben Ashbaugh , Hema Nalluri , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Abhishek R. Appu , Joydeep Ray , Travis Schluessler
Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.
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公开(公告)号：US20200219223A1
公开(公告)日：2020-07-09
申请号：US16243624
申请日：2019-01-09
Applicant: Intel Corporation
Inventor： Balaji Vembu , Brandon Fliflet , James Valerio , Michael Apodaca , Ben Ashbaugh , Hema Nalluri , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Abhishek R. Appu , Joydeep Ray , Travis Schluessler
Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.
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公开(公告)号：US11907756B2
公开(公告)日：2024-02-20
申请号：US16796836
申请日：2020-02-20
Applicant: Intel Corporation
Inventor： Bartosz Dunajski , Brandon Fliflet , Michal Mrozek
CPC classification number: G06F9/4881 , G06F9/30003 , G06F9/3009 , G06F9/4482 , G06F9/485 , G06F9/544 , G06F9/546 , G06T1/20 , G06F9/505 , G06F9/5044 , G06T1/60
Abstract: A graphics processing apparatus that includes at least a memory device and an execution unit coupled to the memory. The memory device can store a command buffer with at least one command that is dependent on completion of at least one other command. The command buffer can include a jump command that causes a jump to a location in the command buffer to identify any unscheduled command. The execution unit is to jump to a location in the command buffer based on execution of the jump command. The execution unit is to perform one or more jumps to one or more locations in the command buffer to attempt to schedule a command with dependency on completion of at least one other command until the command with a dependency on completion of at least one other command is scheduled.
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公开(公告)号：US20220156879A1
公开(公告)日：2022-05-19
申请号：US16951217
申请日：2020-11-18
Applicant: Intel Corporation
Inventor： Michal Mrozek , Bartosz Dunajski , Ben Ashbaugh , Brandon Fliflet
Abstract: An apparatus to facilitate processing in a multi-tile device is disclosed. The apparatus comprises a plurality of processing tiles, each including a memory device and a plurality of processing resources, coupled to the device memory, and a memory management unit to manage the memory devices in each of the plurality of tiles to perform allocation of memory resources among the memory devices for execution by the plurality of processing resources.
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