System and method to support multiple walkers per command

    公开(公告)号:US10776897B1

    公开(公告)日:2020-09-15

    申请号:US16297129

    申请日:2019-03-08

    申请人: Intel Corporation

    IPC分类号: G06T1/20 G06T1/60

    摘要: Embodiments described herein provide an apparatus comprising a processor to configure a plurality of contexts of a command engine to execute a graphics workload comprising a plurality of walkers, allocate, from a pool of execution units of a graphics processor, a subset of execution units to each walker in the plurality of walkers based at least in part on the predetermined number of walkers configured for the context, for each context in the plurality of contexts, dispatch one or more walkers of the plurality of walkers to the execution units, and upon dispatch of the one or more walkers of the plurality of walkers, write an opcode to a computer-readable memory indicating that the dispatch of the walker is complete, wherein the opcode comprises dependency data for the one or more walkers of the plurality of walkers. Other embodiments may be described and claimed.

    MULTI-TILE GRAPHICS PROCESSING UNIT

    公开(公告)号:US20230051227A1

    公开(公告)日:2023-02-16

    申请号:US17978426

    申请日:2022-11-01

    申请人: Intel Corporation

    IPC分类号: G06T1/60 G06T1/20 G06F3/06

    摘要: An apparatus to facilitate processing in a multi-tile device is disclosed. In one embodiment, the apparatus includes a graphics processor comprising a first semiconductor die including a first high-bandwidth memory (HBM) device, a second semiconductor die including a second HBM device, and a third semiconductor die coupled with the first semiconductor die and the second semiconductor die in a 2.5-dimensional (2.5D) arrangement. The third semiconductor die includes a graphics processing resource and a cache coupled with the graphics processing resource. The cache is configurable to cache data associated with memory accessed by the graphics processing resource and the graphics processing resource includes a general-purpose graphics processor core and a tensor core.