公开(公告)号：US20220308876A1

公开(公告)日：2022-09-29

申请号：US17214698

申请日：2021-03-26

申请人： Intel Corporation

发明人： Sudhanshu Shukla ,  Jayesh Gaur ,  Stanislav Shwartsman ,  Pavel I. Kryukov

IPC分类号： G06F9/30 ,  G06F9/38

摘要： Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.

公开(公告)号：US12086591B2

公开(公告)日：2024-09-10

申请号：US17214698

申请日：2021-03-26

申请人： Intel Corporation

发明人： Sudhanshu Shukla ,  Jayesh Gaur ,  Stanislav Shwartsman ,  Pavel I. Kryukov

IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3856

摘要： Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.

公开(公告)号：US20180137053A1

公开(公告)日：2018-05-17

申请号：US15352272

申请日：2016-11-15

申请人： INTEL CORPORATION

发明人： Pavel I. Kryukov ,  Stanislav Shwartsman ,  Joseph Nuzman ,  Alexandr Titov

IPC分类号： G06F12/0808 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891

CPC分类号： G06F12/0808 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/502 ,  G06F2212/6042

摘要： An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.

公开(公告)号：US20230205699A1

公开(公告)日：2023-06-29

申请号：US17561831

申请日：2021-12-24

申请人： Intel Corporation

发明人： Swaraj Sha ,  Anant Vithal Nori ,  Sreenivas Subramoney ,  Stanislav Shwartsman ,  Pavel I. Kryukov ,  Lihu Rappoport

IPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0877 ,  G06F9/38

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0877 ,  G06F9/3816

摘要： An apparatus includes memory circuitry including a first data structure and prefetch circuitry that is coupled to the memory circuitry. The prefetch circuitry is to store, in the first data structure, a first subregion entry corresponding to a first subregion of a memory region allocated to a program. The first subregion entry is to include a plurality of delta values. A first delta value of the plurality of delta values represents a first distance between two cache lines associated with consecutive memory accesses within a second subregion of the memory region. The prefetch circuitry is further to detect a first memory access of a first cache line in the first subregion, identify prefetch candidates based on the first cache line and the plurality of delta values, and issue at least one prefetch request based on at least two of the prefetch candidates to be prefetched into a cache.

公开(公告)号：US09552169B2

公开(公告)日：2017-01-24

申请号：US14706936

申请日：2015-05-07

申请人： INTEL CORPORATION

发明人： Lihu Rappoport ,  Jared W. Stark ,  Kamil Garifullin ,  Franck Sala ,  Pavel I. Kryukov ,  Stanislav Shwartsman

IPC分类号： G06F3/06 ,  G06F12/08

CPC分类号： G06F3/0631 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/0671 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/384 ,  G06F12/0802

摘要： A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.

摘要翻译： 描述了使用虚拟寄存器进行有效的存储器重命名预测的方法和装置。 例如，设备的一个实施例包括：存储器执行单元（MEU），用于执行存储和加载操作，以分别将存储数据存储到存储器中并从存储器加载数据; 分配给存储和加载操作的多个存储器重命名（MRN）寄存器，每个MRN寄存器存储与存储操作相关联的数据，使得数据可用于后续加载操作; 以及至少一个MRN预测器，其包括用于向每个MRN寄存器分配虚拟存储器重命名（VMRN）寄存器的数据结构，MRN预测器，使用标识MRN的值来响应于负载和/或存储操作来查询数据结构 分配给负载和/或存储操作的寄存器，以确定与负载和/或存储操作相关联的当前VMRN寄存器。

公开(公告)号：US10761844B2

公开(公告)日：2020-09-01

申请号：US16023407

申请日：2018-06-29

申请人： Intel Corporation

发明人： Manjunath Shevgoor ,  Mark J. Dechene ,  Stanislav Shwartsman ,  Pavel I. Kryukov

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/1027

摘要： Disclosed embodiments relate to predicting load data. In one example, a processor a pipeline having stages ordered as fetch, decode, allocate, write back, and commit, a training table to store an address, predicted data, a state, and a count of instances of unchanged return data, and tracking circuitry to determine, during one or more of the allocate and decode stages, whether a training table entry has a first state and matches a fetched first load instruction, and, if so, using the data predicted by the entry during the execute stage, the tracking circuitry further to update the training table during or after the write back stage to set the state of the first load instruction in the training table to the first state when the count reaches a first threshold.

公开(公告)号：US10133669B2

公开(公告)日：2018-11-20

申请号：US15352272

申请日：2016-11-15

申请人： INTEL CORPORATION

发明人： Pavel I. Kryukov ,  Stanislav Shwartsman ,  Joseph Nuzman ,  Alexandr Titov

IPC分类号： G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891

摘要： An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.

公开(公告)号：US10095522B2

公开(公告)日：2018-10-09

申请号：US14581268

申请日：2014-12-23

申请人： Intel Corporation

发明人： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30

摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.