公开(公告)号：US20220150006A1

公开(公告)日：2022-05-12

申请号：US17093679

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Michael SHUSTERMAN ,  John FALLIN ,  Ana M. YEPES ,  Dong-Ho HAN ,  Nasser A. KURD ,  Tomer LEVY ,  Ehud RESHEF ,  Arik GIHON ,  Ido OUZIELI ,  Yevgeni SABIN ,  Maor TAL ,  Zhongsheng WANG ,  Amit ZEEVI

IPC: H04L5/00 ,  H04W72/04

Abstract: A wireless communication device for communicating across a wireless communication channel includes one or more processors configured to determine whether a further device is generating a radio frequency interference at an operating frequency; transmit a request message to the further device requesting the further device vacate the operating frequency based on the determination that the further device is generating radio frequency interference; receive a response message from the further device; and generate an instruction based on the response message.

公开(公告)号：US20220121263A1

公开(公告)日：2022-04-21

申请号：US17561651

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Christopher P. MOZAK ,  Robert J. ROYER, Jr. ,  Aaron MARTIN ,  Alex P. THOMAS ,  Tomer LEVY ,  Noam LUPOVICH

IPC: G06F1/3237 ,  G06F1/3234

Abstract: In a memory subsystem, a memory controller can put its physical interface (PHY) into a low power state when an associated memory device is in self-refresh. Instead of powering on the interface and then triggering the memory device to exit self-refresh, or instead waiting for the physical interface to be powered up prior to waking the memory device from self-refresh, the memory controller can instruct the PHY to send a self-refresh exit command to the memory device and power up the physical interface in parallel with the memory device coming out of self-refresh. The memory controller can power down a high speed clock path of the PHY and use a slower clock path to send the self-refresh exit command before powering the high speed clock path back up.

公开(公告)号：US20180025773A1

公开(公告)日：2018-01-25

申请号：US15639725

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  John B. HALBERT ,  Nadav BONEN ,  Tomer LEVY

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4087

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

公开(公告)号：US20170256325A1

公开(公告)日：2017-09-07

申请号：US15057685

申请日：2016-03-01

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Timothy J. CALLAHAN ,  Tomer LEVY

IPC: G11C29/38 ,  G06F13/40 ,  G11C29/44 ,  G06F12/10

CPC classification number: G11C29/38 ,  G06F12/0292 ,  G06F12/10 ,  G06F13/4022 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C29/14 ,  G11C29/16 ,  G11C29/40 ,  G11C29/44 ,  G11C2029/0401

Abstract: A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.

公开(公告)号：US20220262428A1

公开(公告)日：2022-08-18

申请号：US17738923

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Jongwon LEE ,  Tomer LEVY ,  Bill NALE ,  Amir Ali RADJAI

IPC: G11C11/406 ,  G11C11/4078 ,  G11C11/4096

Abstract: Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and/or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT_n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and/or recovery.