公开(公告)号：US11922172B2

公开(公告)日：2024-03-05

申请号：US17028315

申请日：2020-09-22

Applicant: Intel Corporation

Inventor： Karunakara Kotary ,  Pannerkumar Rajagopal ,  Satish Muthiyalu ,  Rajesh Poornachandran

IPC: G06F9/4401 ,  G06F1/3212 ,  G06F9/445 ,  G06F9/451 ,  G06F11/30 ,  G06F11/34 ,  G06F12/0873 ,  G06F13/16 ,  G06F13/40 ,  G11C11/406

CPC classification number: G06F9/4403 ,  G06F1/3212 ,  G06F9/44505 ,  G06F9/451 ,  G06F11/3037 ,  G06F11/3409 ,  G06F12/0873 ,  G06F13/1668 ,  G06F13/4081 ,  G11C11/40622

Abstract: Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.

公开(公告)号：US09535782B2

公开(公告)日：2017-01-03

申请号：US14428338

申请日：2014-04-16

Applicant: Intel Corporation

Inventor： Anil Agrawal ,  Satish Muthiyalu ,  Yingwen Chen ,  Meera Ganesan

IPC: G06F11/00 ,  G06F11/07 ,  G11C29/52 ,  G06F3/06 ,  G11C29/04

CPC classification number: G06F11/0793 ,  G06F3/0614 ,  G06F3/0652 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/106 ,  G11C29/52 ,  G11C2029/0409

Abstract: Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

Abstract translation: 用于为包括一个或多个备用存储器段的存储器的平台提供错误检测和校正的技术和机制。 在一个实施例中，存储器控制器执行包括对多个当前活动存储器段中的错误的检测的第一擦除操作。 对一个或多个存储器段执行附加的巡检擦除，同时存储器段可用作激活作为替换存储器段。 在另一个实施例中，如果基于活动段擦除检测到不可校正的错误事件，则发信号通知第一处理程序进程（但不是第二处理程序进程），而如果不可校正的第二处理程序进程（但不是第一处理程序进程） 基于备用段擦除检测错误事件。 在第一个处理程序进程和第二个处理程序进程中，只有第一个处理程序进程的信号会导致平台的崩溃事件。

公开(公告)号：US11481294B2

公开(公告)日：2022-10-25

申请号：US17262696

申请日：2018-09-15

Applicant: INTEL CORPORATION

Inventor： Satish Muthiyalu ,  Yingwen Chen ,  Yu Yu ,  Tao Xu

IPC: G06F11/20 ,  G11C29/00 ,  G06F13/24 ,  G06F11/16 ,  G11C29/44

Abstract: Runtime memory cell row defect detection and replacement includes detecting in a memory of a computer system operating in a runtime operating system mode, a defective row of memory cells having at least one defective cell. In response to the detection of the defective row, interrupting the operating system of the computer system and, in a runtime system maintenance mode, replacing the defective row of memory cells with a spare row of memory cells as a replacement row of memory cells. Execution of the operating system is then resumed in the runtime operating system mode Other aspects and advantages are described.

公开(公告)号：US20160004587A1

公开(公告)日：2016-01-07

申请号：US14428338

申请日：2014-04-16

Applicant: INTEL CORPORATION

Inventor： Anil Agrawal ,  Satish Muthiyalu ,  Yingwen Chen ,  Meera Ganesan

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0614 ,  G06F3/0652 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/106 ,  G11C29/52 ,  G11C2029/0409

Abstract: Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

Abstract translation: 用于为包括一个或多个备用存储器段的存储器的平台提供错误检测和校正的技术和机制。 在一个实施例中，存储器控制器执行包括对多个当前活动存储器段中的错误的检测的第一擦除操作。 对一个或多个存储器段执行附加的巡检擦除，同时存储器段可用作激活作为替换存储器段。 在另一个实施例中，如果基于活动段擦除检测到不可校正的错误事件，则发信号通知第一处理程序进程（但不是第二处理程序进程），而如果不可校正的第二处理程序进程（但不是第一处理程序进程） 基于备用段擦除检测错误事件。 在第一个处理程序进程和第二个处理程序进程中，只有第一个处理程序进程的信号会导致平台的崩溃事件。

公开(公告)号：US20210026649A1

公开(公告)日：2021-01-28

申请号：US17028315

申请日：2020-09-22

Applicant: Intel Corporation

Inventor： Karunakara Kotary ,  Pannerkumar Rajagopal ,  Satish Muthiyalu ,  Rajesh Poornachandran

IPC: G06F9/4401 ,  G06F9/451 ,  G06F9/445 ,  G06F12/0873 ,  G06F11/30 ,  G06F11/34 ,  G06F13/16 ,  G06F13/40 ,  G06F1/3212 ,  G11C11/406

Abstract: Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.