公开(公告)号：US12253899B2

公开(公告)日：2025-03-18

申请号：US17681988

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Uma Shankar ,  Madhav Singh Chauhan ,  Susanta Bhattacharjee ,  Animesh Manna ,  Vandita Kulkarni ,  Mahesh Kumar

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06T1/60

Abstract: A number of frames may be transferred in one frame period to a display panel followed by at least one frame period during which no frame is transferred. During this link idle time, the display panel continues to work on the transferred frames. However, the link and/or graphics processor may be powered down during this time to reduce power consumption.

公开(公告)号：US10902824B2

公开(公告)日：2021-01-26

申请号：US15494593

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Madhav S. Chauhan ,  Susanta Bhattacharjee ,  Animesh Manna

IPC: G06T1/20 ,  G09G5/391 ,  G09G5/36 ,  G09G3/00 ,  G09G5/02 ,  G06F3/147 ,  G09G5/00

Abstract: If the picture complexity is low then the number of pixels in a frame may be reduced. For example, pixel-to-pixel variation in terms of RGB color values can be used to determine the complexity of the frame. Frames can be characterized, in one embodiment, as non-complex frames with less pixel variation and complex frames with very high pixel variation. The high PPI may be used only for complex frames while non-complex frames can use low PPI. This method reduces memory fetching and pixel processing within the display engine and thereby saves power.

公开(公告)号：US20180286306A1

公开(公告)日：2018-10-04

申请号：US15477041

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Madhav Singh Chauhan ,  Animesh Manna ,  Susanta Bhattacharjee

IPC: G09G3/3233 ,  G09G3/3283 ,  G06F1/32

CPC classification number: G06F1/3265 ,  G06F1/3212 ,  G09G3/3208 ,  G09G3/3406 ,  G09G5/005 ,  G09G5/363 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/024 ,  G09G2350/00 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2360/18 ,  G09G2370/16

Abstract: Methods and apparatus relating to techniques to provide dynamic pixel density adjustment for display panels not driven by backlight are described. In an embodiment, logic causes a first plurality of pixels of a display panel to be turned off in response to an indication that a charge level of a power supply, coupled to supply electrical power to the display panel, has dropped below a threshold level. The display panel is not backlight drive (such as an OLED or QDOT display panels. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220214736A1

公开(公告)日：2022-07-07

申请号：US17681988

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Uma Shankar ,  Madhav Singh Chauhan ,  Susanta Bhattacharjee ,  Animesh Manna ,  Vandita Kulkarni ,  Mahesh Kumar

IPC: G06F1/324 ,  G06T1/60 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3287

Abstract: A number of frames may be transferred in one frame period to a display panel followed by at least one frame period during which no frame is transferred. During this link idle time, the display panel continues to work on the transferred frames. However, the link and/or graphics processor may be powered down during this time to reduce power consumption.

公开(公告)号：US20180308194A1

公开(公告)日：2018-10-25

申请号：US15493191

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Uma Shankar ,  Madhav Singh Chauhan ,  Susanta Bhattacharjee ,  Animesh Manna ,  Vandita Kulkarni ,  Mahesh Kumar

IPC: G06T1/20 ,  G06T1/60 ,  G06F1/32

CPC classification number: G06T1/20 ,  G06F1/324 ,  G06F1/3265 ,  G06F1/3296 ,  G06T1/60

Abstract: A number of frames may be transferred in one frame period to a display panel followed by at least one frame period during which no frame is transferred. During this link idle time, the display panel continues to work on the transferred frames. However, the link and/or graphics processor may be powered down during this time to reduce power consumption.

公开(公告)号：US10372196B2

公开(公告)日：2019-08-06

申请号：US15477041

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Madhav Singh Chauhan ,  Animesh Manna ,  Susanta Bhattacharjee

IPC: G06F1/3234 ,  G06F1/3212 ,  G09G3/34 ,  G09G5/00 ,  G09G5/36 ,  G09G3/3208

Abstract: Methods and apparatus relating to techniques to provide dynamic pixel density adjustment for display panels not driven by backlight are described. In an embodiment, logic causes a first plurality of pixels of a display panel to be turned off in response to an indication that a charge level of a power supply, coupled to supply electrical power to the display panel, has dropped below a threshold level. The display panel is not backlight drive (such as an OLED or QDOT display panels. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180308457A1

公开(公告)日：2018-10-25

申请号：US15494593

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Madhav S. Chauhan ,  Susanta Bhattacharjee ,  Animesh Manna

IPC: G09G5/391 ,  G06T7/90 ,  G09G5/36

CPC classification number: G09G5/391 ,  G06T1/20 ,  G06T7/90 ,  G06T2210/52 ,  G09G5/363 ,  G09G2320/0613 ,  G09G2330/021 ,  G09G2340/0442 ,  G09G2340/16

Abstract: If the picture complexity is low then the number of pixels in a frame may be reduced. For example, pixel-to-pixel variation in terms of RGB color values can be used to determine the complexity of the frame. Frames can be characterized, in one embodiment, as non-complex frames with less pixel variation and complex frames with very high pixel variation. The high PPI may be used only for complex frames while non-complex frames can use low PPI. This method reduces memory fetching and pixel processing within the display engine and thereby saves power.

公开(公告)号：US20220301525A1

公开(公告)日：2022-09-22

申请号：US17831213

申请日：2022-06-02

Applicant: Intel Corporation

Inventor： Krishna Kishore Nidamanuri ,  Animesh Manna ,  Karthik B S

IPC: G09G5/393 ,  G09G5/18

Abstract: In one embodiment, a display system includes circuitry to, after an exit from a self-refresh state, obtain first frame data with a first refresh rate and second frame data with a second refresh rate different than the first refresh rate, and based on the second refresh rate being greater than the first refresh rate, determine an amount of drift between timing controller circuitry of a graphics controller and timing controller circuitry of a display panel, and based on the amount of drift being above a threshold value, cause the first frame data to not be displayed and cause the second frame data to be displayed at the first refresh rate.

公开(公告)号：US11301025B2

公开(公告)日：2022-04-12

申请号：US16952640

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Uma Shankar ,  Madhav Singh Chauhan ,  Susanta Bhattacharjee ,  Animesh Manna ,  Vandita Kulkarni ,  Mahesh Kumar

IPC: G06F1/324 ,  G06T1/60 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3287

Abstract: A number of frames may be transferred in one frame period to a display panel followed by at least one frame period during which no frame is transferred. During this link idle time, the display panel continues to work on the transferred frames. However, the link and/or graphics processor may be powered down during this time to reduce power consumption.

公开(公告)号：US20210141434A1

公开(公告)日：2021-05-13

申请号：US16952640

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Uma Shankar ,  Madhav Singh Chauhan ,  Susanta Bhattacharjee ,  Animesh Manna ,  Vandita Kulkarni ,  Mahesh Kumar

IPC: G06F1/324 ,  G06T1/60 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3287

Abstract: A number of frames may be transferred in one frame period to a display panel followed by at least one frame period during which no frame is transferred. During this link idle time, the display panel continues to work on the transferred frames. However, the link and/or graphics processor may be powered down during this time to reduce power consumption.