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公开(公告)号：US20220361328A1
公开(公告)日：2022-11-10
申请号：US17871686
申请日：2022-07-22
Applicant: Intel Corporation
Inventor： Xiang LI , Konika GANGULY , Tongyan ZHAI , George VERGIS , Anthony M. CONSTANTINE , Jun LIAO
Abstract: Power conversion modules using compression mount technology (CMT) connectors and associated apparatus and methods. Assemblies include a CMT connector that includes an array of spring-loaded CMT pins or contacts that are configured to contact respective pads on a pair of printed circuit board (PCBs), such as for VR module card or power conversion module and a motherboard. The power conversion modules in combination with the CMT connectors provide several advantages, including, a common VR module/power conversion module/motherboard footprint across OEM platforms and test hardware, just in time VR module attachment for improved inventory management, removable power delivery solution makes the platform more conducive to debug, in field servicing, and platform upgradable for higher power CPU/GPU/XPU.
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公开(公告)号：US20220368047A1
公开(公告)日：2022-11-17
申请号：US17874111
申请日：2022-07-26
Applicant: Intel Corporation
Inventor： George VERGIS , Xiang LI , Jun LIAO , Anthony M. CONSTANTINE , Min Suet LIM , Tongyan ZHAI , Konika GANGULY
Abstract: An adapter card with compression-attached memory modules that can be inserted into a conventional vertical connector enables use of CAMMs in systems with vertical memory module connectors. In one example, an adapter card or riser card includes a printed circuit board (PCB) having an edge to be received by a dual-inline memory module (DIMM) connector. First conductive contacts proximate to the edge of the PCB are to be received by the DIMM connector, enabling the first conductive contacts to couple with contacts of the DIMM connector. Second conductive contacts on a face of the PCB are to couple with a first compression attached memory module (CAMM) via a first compression mount technology (CMT) connector. The adapter card includes conductive traces on or in the PCB between the first conductive contacts and the second conductive contacts to couple the CAMM with the DIMM connector.
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公开(公告)号：US20190006340A1
公开(公告)日：2019-01-03
申请号：US15640148
申请日：2017-06-30
Applicant: Intel Corporation
Inventor： Konika GANGULY , Robert J. ROYER, JR. , Rebecca Z. LOOP , Anthony M. CONSTANTINE , Bilal KHALAF
IPC: H01L25/18 , H01L23/50 , H01L23/498 , G11C14/00
Abstract: An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.
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公开(公告)号：US20180356872A1
公开(公告)日：2018-12-13
申请号：US15719539
申请日：2017-09-28
Applicant: INTEL CORPORATION
Inventor： Myron D. LOEWEN , Andrew W. MORNING-SMITH , Anthony M. CONSTANTINE
Abstract: Provided are devices, systems and methods relating to controller interactions with storage. One embodiment includes an apparatus comprising a controller for communication with a storage device through a signal line, wherein the controller is configured to detect a first signal on the signal line indicating the presence of the storage device on the signal line, and provide a second signal on the signal line to reset the storage device after a detection that the first signal indicates the presence of the storage device. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20220358072A1
公开(公告)日：2022-11-10
申请号：US17874117
申请日：2022-07-26
Applicant: Intel Corporation
Inventor： George VERGIS , Xiang LI , Jun LIAO , Anthony M. CONSTANTINE , Min Suet LIM , Tongyan ZHAI , Konika GANGULY
Abstract: A memory module adapter card can adapt multiple compression-attached memory modules (CAMMs) to a dual inline memory module (DIMM) connector. Multiplexer circuitry on the adapter card enables multiplexing data amongst the memory modules attached to the adapter card during a same burst access sequence.
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6.发明申请公开(公告)号：US20180357187A1
公开(公告)日：2018-12-13
申请号：US15700031
申请日：2017-09-08
Applicant: INTEL CORPORATION
Inventor： Myron D. LOEWEN , Andrew W. MORNING-SMITH , Anthony M. CONSTANTINE
CPC classification number: G06F13/1631 , G06F13/20 , G06F13/4081 , G06F2213/0026 , G06F2213/0052 , H04L12/40169
Abstract: Provided are apparatus, system, and method for positionally aware device management bus address assignment. A presence of a plurality of storage devices is detected on a bus. One of the storage devices detected on the bus is selected. A get identifier command is sent on the bus to all of the storage devices that is only responded to by the selected storage device. A unique identifier is received from the selected storage device over the bus. An address for the selected storage device is assigned and an entry is added to the address mapping to indicate the unique identifier, the assigned address, and a physical location indicator for the selected storage device.
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公开(公告)号：US20230007775A1
公开(公告)日：2023-01-05
申请号：US17871542
申请日：2022-07-22
Applicant: Intel Corporation
Inventor： Xiang LI , Konika GANGULY , Tongyan ZHAI , George VERGIS , Anthony M. CONSTANTINE , Jun LIAO
Abstract: Methods and apparatus for GDDR (Graphics Double Date Rate) memory expander using compression mount technology (CMT) connectors. A CMT connector with a dedicated pinout for GDDR-based memory is provided that enables end users and manufacturers to change the amount of GDDR memory provided with a GPU card, accelerator card, or apparatus having other form factors. Memory could also be replaced in the event of a failure. In addition, embodiments are disclosed that support a split channel concept where there could be multiple devices (e.g., GDDR modules) with dedicated signals routed to each module.
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公开(公告)号：US20220360002A1
公开(公告)日：2022-11-10
申请号：US17871611
申请日：2022-07-22
Applicant: Intel Corporation
Inventor： Xiang LI , Konika GANGULY , Tongyan ZHAI , George VERGIS , Anthony M. CONSTANTINE , Jun LIAO
Abstract: Methods and apparatus for differential I/O (input/output) cards using compression mount technology (CMT) connectors. Assemblies include a CMT connector having an array of spring-loaded pins or contacts that are configured to contact respective CMT contact pads on a pair of printed circuit board (PCBs), such as an add-in card (AIC) and a motherboard. Stacked assemblies are also disclosed including multiple CMT AIC or PCIe modules communicatively coupled using on module CMT connectors. The connector solutions may be used for AICs without changing the overall PCB form factor outline of existing AICs employing edge connectors. Under a stacked assembly of multiple CMT PCIe modules interconnected by on module CMT connectors, wiring in the PCBs is configured to provide signaling supporting multi-lane PCIe or CXL links for each CMT PCIe module. The CMT connector approach also is scalable and can support more pins/contacts to facilitate additional I/O bandwidth.
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公开(公告)号：US20180285307A1
公开(公告)日：2018-10-04
申请号：US15476882
申请日：2017-03-31
Applicant: INTEL CORPORATION
Inventor： Daniel S. WILLIS , Anthony M. CONSTANTINE
Abstract: Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.
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