公开(公告)号：US20220100696A1

公开(公告)日：2022-03-31

申请号：US17466371

申请日：2021-09-03

Applicant: INTEL CORPORATION

Inventor： ELIEZER TAMIR ,  VADIM MAKHERVAKS ,  BEN-ZION FRIEDMAN ,  PHIL CAYTON ,  THEODORE L. WILLKE

IPC: G06F15/173 ,  G06F21/44 ,  G06F21/79 ,  H04L29/06 ,  G06F3/06 ,  G06F21/80 ,  G06F15/167 ,  H04L29/08 ,  G06F13/42

Abstract: Examples are disclosed for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may allocate, in a memory of the server, a buffer, a doorbell, and a queue pair accessible to a client remote to the server. For these examples, the network input/output device may assign an Non-Volatile Memory Express (NVMe) namespace context to the client. For these examples, indications of the allocated buffer, doorbell, queue pair, and namespace context may be transmitted to the client. Other examples are described and claimed.

公开(公告)号：US20170212762A1

公开(公告)日：2017-07-27

申请号：US15425908

申请日：2017-02-06

Applicant: Intel Corporation

Inventor： ELIEZER TAMIR ,  BEN-ZION FRIEDMAN

IPC: G06F9/38 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F9/3861 ,  G06F1/32 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/3802 ,  G06F9/3867 ,  G06F9/46 ,  G06F9/5038 ,  G06F9/5044 ,  Y02D10/122 ,  Y02D10/24 ,  Y02D50/20

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

公开(公告)号：US20190278739A1

公开(公告)日：2019-09-12

申请号：US16426685

申请日：2019-05-30

Applicant: INTEL CORPORATION

Inventor： ELIEZER TAMIR ,  VADIM MAKHERVAKS ,  BEN-ZION FRIEDMAN ,  PHIL CAYTON ,  THEODORE L. WILLKE

IPC: G06F15/173 ,  H04L29/08 ,  G06F21/80 ,  H04L29/06 ,  G06F13/42 ,  G06F3/06 ,  G06F15/167 ,  G06F21/79 ,  G06F21/44

Abstract: Examples are disclosed for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may allocate, in a memory of the server, a buffer, a doorbell, and a queue pair accessible to a client remote to the server. For these examples, the network input/output device may assign an Non-Volatile Memory Express (NVMe) namespace context to the client. For these examples, indications of the allocated buffer, doorbell, queue pair, and namespace context may be transmitted to the client. Other examples are described and claimed.

公开(公告)号：US20190278609A1

公开(公告)日：2019-09-12

申请号：US16358154

申请日：2019-03-19

Applicant: INTEL CORPORATION

Inventor： ELIEZER TAMIR ,  BEN-ZION FRIEDMAN

IPC: G06F9/38 ,  G06F9/50 ,  G06F1/32 ,  G06F9/46 ,  G06F1/3293 ,  G06F1/329

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

公开(公告)号：US20180091369A1

公开(公告)日：2018-03-29

申请号：US15279386

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： ANDREW CUNNINGHAM ,  BEN-ZION FRIEDMAN ,  JOHN BROWNE ,  ROBIN GILLER ,  ALEXANDER LECKEY ,  ELIEZER TAMIR

IPC: H04L12/24 ,  H04L12/26

CPC classification number: H04L41/0816 ,  H04L41/0672 ,  H04L43/0888 ,  H04L43/16

Abstract: Embodiments may be generally directed to techniques to receive rate meter information indicating an occurrence of a rate meter event, the rate meter event determined by a rate meter associated with a network element in a software defined network (SDN) environment. determine a requirement for a service provided by the network element is not met based on the rate meter event detected by the rate meter. Embodiments may also include techniques to determine a corrective action based on the requirement not met, the corrective action to cause the requirement to be met for the service provided by the network element in the SDN environment and cause the correct action to be performed for the network element.

公开(公告)号：US20160188344A1

公开(公告)日：2016-06-30

申请号：US14583308

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： ELIEZER TAMIR ,  BEN-ZION FRIEDMAN

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F1/32 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/3802 ,  G06F9/3867 ,  G06F9/46 ,  G06F9/5038 ,  G06F9/5044 ,  Y02D10/122 ,  Y02D10/24 ,  Y02D50/20

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及用于较高功能核心和较低功率核心之间的协作的技术，以最小化中断对当前指令执行流的影响。 装置可以包括：包括第一指令流水线的下功率核心，低功率核心，用于停止第一指令流水线中的第一执行流程，并且执行第一指令流水线中的处理程序例程的指令，以执行第一任务处理 打断; 以及包括第二指令流水线的较高功能核心，所述较高功能核心在执行所述第一任务之后，调度在所述第二指令流水线中处理所述中断的第二任务的指令的执行，以遵循第二指令流程 第二条指令管道，第一个任务比第二个任务更时间敏感。 描述和要求保护其他实施例。