公开(公告)号：US20160328335A1

公开(公告)日：2016-11-10

申请号：US14703420

申请日：2015-05-04

申请人： Intel Corporation

发明人： BINATA BHATTACHARYYA ,  AMY L. SANTONI ,  RAGHUNANDAN MAKARAM ,  FRANCIS X. MCKEEN ,  SIMON P. JOHNSON ,  GEORGE Z. CHRYSOS ,  SIDDHARTHA CHHABRA

IPC分类号： G06F12/14 ,  H04L9/08

CPC分类号： H04L9/3242 ,  H04L9/0637 ,  H04L2209/12

摘要： Systems and methods for memory protection for implementing trusted execution environment. An example processing system comprises: an on-package memory; a memory encryption engine (MEE) comprising a MEE cache, the MEE to: responsive to failing to locate, within the MEE cache, an encryption metadata associated with a data item loaded from an external memory, retrieve at least part of the encryption metadata from the OPM, and validate the data item using the encryption metadata.

摘要翻译： 用于实现可信执行环境的内存保护的系统和方法。 一个示例性处理系统包括：一个包装内存储器; 包括MEE缓存的存储器加密引擎（MEE），所述MEE响应于在所述MEE缓存内未能定位与从外部存储器加载的数据项相关联的加密元数据，从所述MEE缓存中检索至少部分所述加密元数据 OPM，并使用加密元数据验证数据项。

公开(公告)号：US20230400908A1

公开(公告)日：2023-12-14

申请号：US18196309

申请日：2023-05-11

申请人： Intel Corporation

发明人： BINATA BHATTACHARYYA ,  PAUL S. DIEFENBAUGH

IPC分类号： G06F1/3287 ,  G06F1/3206 ,  G06F3/06 ,  G06F9/30 ,  G06F12/06

CPC分类号： G06F1/3287 ,  G06F1/3206 ,  G06F3/0625 ,  G06F9/30098 ,  G06F12/0607 ,  G06F3/064 ,  G06F3/0679

摘要： Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

公开(公告)号：US20220066535A1

公开(公告)日：2022-03-03

申请号：US17522294

申请日：2021-11-09

申请人： Intel Corporation

发明人： BINATA BHATTACHARYYA ,  PAUL S. DIEFENBAUGH

IPC分类号： G06F1/3287 ,  G06F1/3206 ,  G06F3/06 ,  G06F9/30 ,  G06F12/06

摘要： Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

公开(公告)号：US20170017296A1

公开(公告)日：2017-01-19

申请号：US15277944

申请日：2016-09-27

申请人： Intel Corporation

发明人： JAYAKRISHNA G. GUDDETI ,  BINATA BHATTACHARYYA

IPC分类号： G06F1/32 ,  G06F13/24 ,  G06F9/44

CPC分类号： G06F1/3287 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/4418 ,  G06F13/24 ,  Y02D10/24 ,  Y02D50/20

摘要： An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread.

摘要翻译： 本文描述了一种在产生新线程之前提供早期唤醒方案的装置和方法。 早期的唤醒指示可以在新的线程被产生之前提供一定的时间量，其可以包括执行从当前功率状态降级到更靠近有功功率状态的较低功率状态的时间量 并在处理元件（例如，核心或线程）上执行。 在遇到诸如辅助线程的新线程的产生时，处理元件可以进一步从较低功率状态转换到有功功率状态。 可以在处理元件上执行新线程，而不会在新线程的产生之后产生等待从当前功率状态到有功功率状态的新线程的执行相关联的延迟。

公开(公告)号：US20160275018A1

公开(公告)日：2016-09-22

申请号：US14661044

申请日：2015-03-18

申请人： Intel Corporation

发明人： SIDDHARTHA CHHABRA ,  RAGHUNANDAN MAKARAM ,  JIM MCCORMICK ,  BINATA BHATTACHARYYA

IPC分类号： G06F12/14 ,  G06F12/08

CPC分类号： G06F21/79

摘要： This disclosure is directed to cache and data organization for memory protection. Memory protection operations in a device may be expedited by organizing cache and/or data structure while providing memory protection for encrypted data. An example device may comprise processing module and a memory module. The processing module may include a memory encryption engine (MEE) to decrypt encrypted data loaded from the memory module, or to encrypt plaintext data prior to storage in the memory module, using security metadata also stored in the memory module. Example security metadata may include version (VER) data, memory authentication code (MAC) data and counter data. Consistent with the present disclosure, a cache associated with the MEE may be partitioned to separate the VER and MAC data from counter data. Data organization may comprise including the VER and MAC data corresponding to particular data in the same data line.

摘要翻译： 本公开涉及用于存储器保护的缓存和数据组织。 可以通过组织高速缓存和/或数据结构同时为加密的数据提供存储器保护来加速设备中的存储器保护操作。 示例设备可以包括处理模块和存储器模块。 处理模块可以包括用于解密从存储器模块加载的加密数据的存储器加密引擎（MEE），或者使用也存储在存储器模块中的安全元数据，在存储在存储器模块中之前加密明文数据。 示例安全元数据可以包括版本（VER）数据，存储器认证码（MAC）数据和计数器数据。 与本公开一致，可以将与MEE相关联的缓存分区以将VER和MAC数据与计数器数据分离。 数据组织可以包括在相同数据线中包括对应于特定数据的VER和MAC数据。