公开(公告)号：US20250081597A1

公开(公告)日：2025-03-06

申请号：US18240106

申请日：2023-08-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Anindya DASGUPTA ,  Ankit Kirit LAKHANI ,  Guanqun CHEN ,  Ian TOLLE ,  Saurabh ACHARYA ,  Shengsi LIU ,  Baofu ZHU ,  Nikhil MEHTA ,  Krishna GANESAN ,  Charles H. WALLACE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

公开(公告)号：US20240113108A1

公开(公告)日：2024-04-04

申请号：US17958285

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Leonard P. GULER ,  Hongqian SUN ,  Shengsi LIU ,  Tahir GHANI ,  Baofu ZHU

IPC: H01L27/088 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a wall within a metal gate cut in a transistor layer of a semiconductor device, where the wall includes a volume of a gas such as air, nitrogen, or another inert gas. Other embodiments may be described and/or claimed.

公开(公告)号：US20250107195A1

公开(公告)日：2025-03-27

申请号：US18373466

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Thomas O’BRIEN ,  Anindya DASGUPTA ,  Shengsi LIU ,  Saurabh ACHARYA ,  Charles H. WALLACE ,  Baofu ZHU

IPC: H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate structure is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure has a first portion laterally spaced apart from the epitaxial source or drain structure, a second portion vertically over the epitaxial source or drain structure, and a third portion between the first portion and the second portion. A dielectric plug is laterally between the epitaxial source or drain structure and the first portion of the conductive trench contact structure, wherein the third portion of the conductive trench contact structure is vertically over the dielectric plug.