公开(公告)号：US20220415791A1

公开(公告)日：2022-12-29

申请号：US17357773

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tsuan-Chung CHANG ,  Michael James MAKOWSKI ,  Benjamin KRIEGEL ,  Robert JOACHIM ,  Desalegne B. TEWELDEBRHAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Mohammad HASAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a dielectric material structure having a trench therein. A conductive interconnect line in the trench, the conductive interconnect line having a length and a width, the width having a cross-sectional profile, wherein the cross-sectional profile of the width of the conductive interconnect line has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width.

公开(公告)号：US20240178226A1

公开(公告)日：2024-05-30

申请号：US18437961

申请日：2024-02-09

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael K. HARPER ,  William HSU ,  Biswajeet GUHA ,  Tahir GHANI ,  Niels ZUSSBLATT ,  Jeffrey Miles TAN ,  Benjamin KRIEGEL ,  Mohit K. HARAN ,  Reken PATEL ,  Oleg GOLONZKA ,  Mohammad HASAN

IPC: H01L27/088 ,  G11C5/06 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G11C5/06 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

公开(公告)号：US20220093592A1

公开(公告)日：2022-03-24

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael K. HARPER ,  William HSU ,  Biswajeet GUHA ,  Tahir GHANI ,  Niels ZUSSSBLATT ,  Jeffrey Miles TAN ,  Benjamin KRIEGEL ,  Mohit K. HARAN ,  Reken PATEL ,  Oleg GOLONZKA ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  G11C5/06

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.