-
公开(公告)号：US20220209794A1
公开(公告)日：2022-06-30
申请号：US17700022
申请日：2022-03-21
申请人： Intel Corporation
摘要： A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.
-
公开(公告)号：US20210117270A1
公开(公告)日：2021-04-22
申请号：US17133995
申请日：2020-12-24
申请人： Intel Corporation
摘要： Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.
-
3.发明申请公开(公告)号：US20200219580A1
公开(公告)日：2020-07-09
申请号：US16827235
申请日：2020-03-23
申请人： Intel Corporation
IPC分类号： G11C29/42 , G11C29/44 , G11C29/02 , G11C11/409 , G11C5/02
摘要： Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.
-
公开(公告)号：US20210111738A1
公开(公告)日：2021-04-15
申请号：US17130697
申请日：2020-12-22
申请人： Intel Corporation
摘要： A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
-
公开(公告)号：US20210013903A1
公开(公告)日：2021-01-14
申请号：US17032567
申请日：2020-09-25
申请人： Intel Corporation
摘要： Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.
-
公开(公告)号：US20190140660A1
公开(公告)日：2019-05-09
申请号：US16242155
申请日：2019-01-08
申请人： Intel Corporation
CPC分类号： H03M13/1125 , G06F11/1012 , G06F11/1048 , G06F11/1068 , G11C29/04 , G11C2029/0411 , H03M13/1117 , H03M13/112 , H03M13/3723 , H03M13/6325 , H03M13/658
摘要： Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuity to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct. When a correct decoded codeword is not produced using predetermined LLRs, further logic may be executed to estimate the LLRs for a plurality of buckets of the plurality of dies, normalize magnitudes of the estimated LLRs, decode the encoded codeword using the normalized estimated LLRs to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the normalized estimated LLRs when the decoded codeword is not correct, up to a second number of times when the decoded codeword is not correct.
-
7.发明申请USING READ VALUES FROM PREVIOUS DECODING OPERATIONS TO CALCULATE SOFT BIT INFORMATION IN AN ERROR RECOVERY OPERATION 有权在以前的解码操作中使用读取值来计算错误恢复操作中的软信息公开(公告)号：US20150095736A1
公开(公告)日：2015-04-02
申请号：US14040554
申请日：2013-09-27
申请人： Intel Corporation
发明人： Lark-Hoon LEEM , Xin GUO , Ravi H. MOTWANI , Rosanna YEE , Scott E. NELSON
IPC分类号： G06F11/10
CPC分类号： G06F11/141 , G06F11/1012
摘要： Provided are an apparatus, system, and method for performing an error recovery operation with respect to a read of a block of memory cells in a storage device. A current iteration of a decoding operation is performed by applying at least one reference voltage for the current iteration to a block of the memory cells in the storage device to determine current read values in response to applying the reference voltage. A symbol is generated for each of the read memory cells by combining the determined current read value with at least one value saved during the previous iteration. The symbols are used to determine bit reliability metrics for the block of memory cells. The bit reliability metrics are decoded. In response to the decoding failing, an additional iteration of the decoding operation is performed.
摘要翻译： 提供了一种用于对存储装置中的存储单元块的读取执行错误恢复操作的装置，系统和方法。 通过对当前迭代中的至少一个参考电压施加到存储装置中的存储器单元的块来执行解码操作的当前迭代，以响应于施加参考电压来确定当前读取值。 通过将确定的当前读取值与在先前迭代中保存的至少一个值组合，为每个读取的存储器单元生成符号。 这些符号用于确定存储器单元块的位可靠性度量。 比特可靠性度量被解码。 响应于解码失败，执行解码操作的附加迭代。
-
公开(公告)号：US20230036512A1
公开(公告)日：2023-02-02
申请号：US17961410
申请日：2022-10-06
申请人： Intel Corporation
IPC分类号： H03M13/11
摘要： A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
-
公开(公告)号：US20210074338A1
公开(公告)日：2021-03-11
申请号：US16562745
申请日：2019-09-06
申请人： Intel Corporation
摘要： Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.
-
10.发明申请公开(公告)号：US20190034269A1
公开(公告)日：2019-01-31
申请号：US15851596
申请日：2017-12-21
申请人： INTEL CORPORATION
发明人： Pranav KALAVADE , Ravi H. MOTWANI
CPC分类号： G06F11/1068 , G11C29/52 , G11C2029/0409 , H03M13/1105 , H03M13/1128 , H03M13/1148
摘要： A non-volatile memory unit receives a request from a controller to read encoded data stored in a non-volatile memory of the non-volatile memory unit. In response to determining by logic included in the non-volatile memory unit that the controller is estimated to be able to successfully decode the encoded data more than a predetermined percentage of times, the encoded data is transferred from the non-volatile memory unit to the controller.
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.015 秒)
