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    CALIBRATION SCHEME FOR IMPROVING FLEXIBILITY ON PLATFORM IMPLEMENTATION
    1.
    发明申请
    CALIBRATION SCHEME FOR IMPROVING FLEXIBILITY ON PLATFORM IMPLEMENTATION 有权
    改进平台实施灵活性的校准方案

    公开(公告)号：US20160282918A1

    公开(公告)日：2016-09-29

    申请号：US14671127

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Chia How Low

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/263 ,  G06F1/3243 ,  G06F1/3253 ,  G06F1/3278 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/157

    Abstract: An apparatus is described herein. The apparatus includes a plurality of electrical components, wherein at least one component is to increase a total impedance at a port. The apparatus also includes a comparator, wherein the comparator is to determine an additional impedance from the plurality of electrical components at the port and adjust the impedance to maintain signal integrity along a trace to the port in response to a device being coupled with the port.

    Abstract translation: 这里描述了一种装置。 该装置包括多个电气部件，其中至少一个部件是增加端口处的总阻抗。 该装置还包括比较器，其中比较器将确定来自端口处的多个电气部件的附加阻抗，并且响应于与端口耦合的装置，调整阻抗以维持沿着到端口的轨迹的信号完整性。

    Apparatuses, methods, and systems for providing a dynamic bias voltage to one or more transistors of a transceiver
    3.
    发明授权
    Apparatuses, methods, and systems for providing a dynamic bias voltage to one or more transistors of a transceiver 有权
    用于向收发器的一个或多个晶体管提供动态偏置电压的装置，方法和系统

    公开(公告)号：US09495002B2

    公开(公告)日：2016-11-15

    申请号：US14270356

    申请日：2014-05-05

    Applicant: Intel Corporation

    Inventor： Chia How Low

    IPC: G06F1/00 ,  G06F1/32 ,  H04B1/38

    CPC classification number: G06F1/3293 ,  G06F1/00 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  H04B1/38

    Abstract: Embodiments include apparatuses, methods, and systems for providing a dynamic bias voltage to one or more transistors of a transceiver. In embodiments, a transceiver includes receive circuitry and transmit circuitry coupled to a same input/output (I/O) pad. A dynamic biasing circuit detects a voltage level of a data signal on the I/O pad, and generates a dynamic bias voltage having a value based on the detected voltage level. In some embodiments, the dynamic bias voltage is a selected one of a first bias voltage or a second bias voltage. The dynamic biasing circuit provides the dynamic bias voltage to one or more transistors of the transceiver to protect the transistors from electrical overstress.

    Abstract translation: 实施例包括用于向收发器的一个或多个晶体管提供动态偏置电压的装置，方法和系统。 在实施例中，收发器包括耦合到相同输入/输出（I / O）垫的接收电路和发送电路。 动态偏置电路检测I / O焊盘上的数据信号的电压电平，并产生具有基于检测到的电压电平的值的动态偏置电压。 在一些实施例中，动态偏置电压是第一偏置电压或第二偏置电压中的选定的一个。 动态偏置电路为收发器的一个或多个晶体管提供动态偏置电压，以保护晶体管免受电力过载。

    LOCALIZED IR DROP DETECTION AND CALIBRATION SCHEME TO CREATE HIGH ACCURACY VOLTAGE SUPPLY ACROSS PHYSICAL CIRCUIT PARTITIONS FOR PERFORMANCE GAIN
    4.
    发明公开
    LOCALIZED IR DROP DETECTION AND CALIBRATION SCHEME TO CREATE HIGH ACCURACY VOLTAGE SUPPLY ACROSS PHYSICAL CIRCUIT PARTITIONS FOR PERFORMANCE GAIN 审中-公开

    公开(公告)号：US20240230725A9

    公开(公告)日：2024-07-11

    申请号：US17972360

    申请日：2022-10-24

    Applicant: Intel Corporation

    Inventor： Chia How Low ,  Roger Cheng

    IPC: G01R19/10

    CPC classification number: G01R19/10

    Abstract: Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.

    LOCALIZED IR DROP DETECTION AND CALIBRATION SCHEME TO CREATE HIGH ACCURACY VOLTAGE SUPPLY ACROSS PHYSICAL CIRCUIT PARTITIONS FOR PERFORMANCE GAIN
    5.
    发明公开
    LOCALIZED IR DROP DETECTION AND CALIBRATION SCHEME TO CREATE HIGH ACCURACY VOLTAGE SUPPLY ACROSS PHYSICAL CIRCUIT PARTITIONS FOR PERFORMANCE GAIN 审中-公开

    公开(公告)号：US20240133925A1

    公开(公告)日：2024-04-25

    申请号：US17972360

    申请日：2022-10-23

    Applicant: Intel Corporation

    Inventor： Chia How Low ,  Roger Cheng

    IPC: G01R19/10

    CPC classification number: G01R19/10

    Abstract: Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.

    DYNAMIC BIASING CIRCUIT FOR TRANSCEIVER
    6.
    发明申请
    DYNAMIC BIASING CIRCUIT FOR TRANSCEIVER 有权
    用于收发器的动态偏置电路

    公开(公告)号：US20150316977A1

    公开(公告)日：2015-11-05

    申请号：US14270356

    申请日：2014-05-05

    Applicant: Intel Corporation

    Inventor： Chia How Low

    IPC: G06F1/32

    CPC classification number: G06F1/3293 ,  G06F1/00 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  H04B1/38

    Abstract: Embodiments include apparatuses, methods, and systems for providing a dynamic bias voltage to one or more transistors of a transceiver. In embodiments, a transceiver may include receive circuitry and transmit circuitry coupled to a same input/output (I/O) pad. A dynamic biasing circuit may detect a voltage level of a data signal on the I/O pad, and may generate a dynamic bias voltage having a value based on the detected voltage level. In some embodiments, the dynamic bias voltage may be a selected one of a first bias voltage or a second bias voltage, The dynamic biasing circuit may provide the dynamic bias voltage to one or more transistors of the transceiver to protect the transistors from electrical overstress.

    Abstract translation: 实施例包括用于向收发器的一个或多个晶体管提供动态偏置电压的装置，方法和系统。 在实施例中，收发器可以包括耦合到相同输入/输出（I / O）垫的接收电路和发送电路。 动态偏置电路可以检测I / O焊盘上的数据信号的电压电平，并且可以产生具有基于检测到的电压电平的值的动态偏置电压。 在一些实施例中，动态偏置电压可以是第一偏置电压或第二偏置电压中的选定的一个。动态偏置电路可以向收发器的一个或多个晶体管提供动态偏置电压，以保护晶体管免受电力过载。

    Apparatuses, systems, and methods for USB high-speed chirp detection
    8.
    发明授权
    Apparatuses, systems, and methods for USB high-speed chirp detection 有权

    公开(公告)号：US10120436B2

    公开(公告)日：2018-11-06

    申请号：US15078886

    申请日：2016-03-23

    Applicant: Intel Corporation

    Inventor： Chia How Low ,  Jia Jun Lee

    IPC: G06F1/32 ,  G06F13/40 ,  G06F13/42

    Abstract: Methods and apparatuses relating to USB high-speed chirp detection are described. In one embodiment, a bus host transceiver circuit includes a first data path to connect to a bus device, a second data path to connect to the bus device, a squelch detection circuit with a first and a second input, and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period.

    Flexible interconnect architecture
    9.
    发明授权
    Flexible interconnect architecture 有权

    公开(公告)号：US09843436B2

    公开(公告)日：2017-12-12

    申请号：US14752856

    申请日：2015-06-27

    Applicant: Intel Corporation

    Inventor： Chia How Low ,  Su Sin Florence Phun

    IPC: H04L5/16 ,  G06F13/40

    CPC classification number: H04L5/16 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A port is provided to facilitate a link between a first device and a second device. The port can include a driver circuit to support half duplex communication between the first device and the second device and further include switching logic to receive a value and cause the driver circuit to function in one of a plurality of half duplex modes based on the value. The value is based on a configuration register value corresponding to the port.

    APPARATUSES, SYSTEMS, AND METHODS FOR USB HIGH-SPEED CHIRP DETECTION
    10.
    发明申请
    APPARATUSES, SYSTEMS, AND METHODS FOR USB HIGH-SPEED CHIRP DETECTION 审中-公开

    公开(公告)号：US20170277249A1

    公开(公告)日：2017-09-28

    申请号：US15078886

    申请日：2016-03-23

    Applicant: Intel Corporation

    Inventor： Chia How Low ,  Jia Jun Lee

    IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40

    CPC classification number: G06F1/3293 ,  G06F1/3296 ,  G06F13/4022 ,  G06F13/4282

    Abstract: Methods and apparatuses relating to USB high-speed chirp detection are described. In one embodiment, a bus host transceiver circuit includes a first data path to connect to a bus device, a second data path to connect to the bus device, a squelch detection circuit with a first and a second input, and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period.

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