公开(公告)号：US10042412B2

公开(公告)日：2018-08-07

申请号：US14563079

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Jia Jun Lee ,  Asad Azam

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/42 ,  G06F9/4401

Abstract: In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background.

公开(公告)号：US20150227489A1

公开(公告)日：2015-08-13

申请号：US14457594

申请日：2014-08-12

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Jia Jun Lee ,  Amit Kumar Srivastava ,  Teong Guan T.G. Yew ,  Tim McKee

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/385

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 该方法包括在一对嵌入式高速串行接口数据线中的每一个上发出单端（SE1）信号，指示寄存器访问协议（RAP）消息的SE1跟随SE1信号。 该方法还包括基于RAP消息访问嵌入式高速串行接口组件的寄存器。

公开(公告)号：US10452599B2

公开(公告)日：2019-10-22

申请号：US15775255

申请日：2016-10-20

Applicant: INTEL CORPORATION

Inventor： Chia How Low ,  Jia Jun Lee ,  Kevin Beow Ee Tan ,  Chee Hong Aw

IPC: G06F13/42 ,  G06F13/40

Abstract: An Embedded Universal Serial Bus 2.0 (USB2) device includes a physical layer having a detection mechanism to detect an Single-ended 1 (SE1) valid state and differentiate the SE1 valid state from other USB2 states.

公开(公告)号：US10120436B2

公开(公告)日：2018-11-06

申请号：US15078886

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Chia How Low ,  Jia Jun Lee

IPC: G06F1/32 ,  G06F13/40 ,  G06F13/42

Abstract: Methods and apparatuses relating to USB high-speed chirp detection are described. In one embodiment, a bus host transceiver circuit includes a first data path to connect to a bus device, a second data path to connect to the bus device, a squelch detection circuit with a first and a second input, and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period.

公开(公告)号：US20180011528A1

公开(公告)日：2018-01-11

申请号：US14563079

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Jia Jun Lee ,  Asad Azam

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/3215 ,  G06F1/3253 ,  G06F1/3278 ,  G06F1/3296 ,  G06F9/4418 ,  G06F13/4282 ,  Y02D10/151 ,  Y02D10/157

Abstract: In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background.

公开(公告)号：US20170277249A1

公开(公告)日：2017-09-28

申请号：US15078886

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Chia How Low ,  Jia Jun Lee

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F1/3293 ,  G06F1/3296 ,  G06F13/4022 ,  G06F13/4282

Abstract: Methods and apparatuses relating to USB high-speed chirp detection are described. In one embodiment, a bus host transceiver circuit includes a first data path to connect to a bus device, a second data path to connect to the bus device, a squelch detection circuit with a first and a second input, and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period.

公开(公告)号：US09606955B2

公开(公告)日：2017-03-28

申请号：US14457594

申请日：2014-08-12

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Jia Jun Lee ,  Amit Kumar Srivastava ,  Teong Guan T. G. Yew ,  Tim McKee

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4291 ,  G06F13/385

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.