公开(公告)号：US20030075787A1

公开(公告)日：2003-04-24

申请号：US10045315

申请日：2001-10-24

Applicant: Intel Corporation

Inventor： Chris Baldwin

IPC: H01L023/02

CPC classification number: H01L23/13 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/1433 ,  H01L2924/15312 ,  H01L2924/19106

Abstract: An electronic package includes an IC, such as a die, mounted onto one side of a thin interposer and a pin carrier mounted to an opposing side of the interposer. The pin carrier includes a cavity underneath the die. The cavity allows capacitors, or other electronic components, to be mounted against the interposer beneath the die. The cavity in the pin carrier is filled with an encapsulant to mechanically support the thin interposer in the area of the cavity during operation of an electronic system that includes the package.

Abstract translation: 电子封装包括安装在薄插入件的一侧上的诸如裸片的IC，以及安装到插入件的相对侧的销托架。 销托架包括在模具下面的空腔。 空腔允许电容器或其他电子部件安装在模具下方的插入件上。 引脚托架中的空腔填充有密封剂，以在包括封装的电子系统的操作期间机械地支撑薄插入件在空腔区域中。

公开(公告)号：US20040241914A1

公开(公告)日：2004-12-02

申请号：US10884654

申请日：2004-07-02

Applicant: Intel Corporation

Inventor： Chris Baldwin

IPC: H01L023/48 ,  H01L021/44 ,  H01L021/50 ,  H01L021/48 ,  H01L023/52

CPC classification number: H01L23/13 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/1433 ,  H01L2924/15312 ,  H01L2924/19106

Abstract: An electronic package includes an IC, such as a die, mounted onto one side of a thin interposer and a pin carrier mounted to an opposing side of the interposer. The pin carrier includes a cavity underneath the die. The cavity allows capacitors, or other electronic components, to be mounted against the interposer beneath the die. The cavity in the pin carrier is filled with an encapsulant to mechanically support the thin interposer in the area of the cavity during operation of an electronic system that includes the package.

Abstract translation: 电子封装包括安装在薄插入件的一侧上的诸如裸片的IC，以及安装到插入件的相对侧的销托架。 销托架包括在模具下面的空腔。 空腔允许电容器或其他电子部件安装在模具下方的插入件上。 引脚托架中的空腔填充有密封剂，以在包括封装的电子系统的操作期间机械地支撑薄插入件在空腔区域中。

公开(公告)号：US20040021215A1

公开(公告)日：2004-02-05

申请号：US10209847

申请日：2002-07-31

Applicant: Intel Corporation

Inventor： Dong Zhong ,  Farzaneh Yahyaei-Moayyed ,  David G. Figueroa ,  Chris Baldwin ,  Jiangqi He ,  Yuan-Liang Li

IPC: H01L023/48 ,  H01L023/52

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

Abstract translation: 包括芯片，电源端子和接地端子的集成电路全部安装在基板上。 所述动力端子包括主体和从所述主体突出的第一延伸部，所述接地端子包括主体和从所述主体突出的第二延伸部。 接地端子上的第二延伸部分与电源端子上的第一延伸部相邻，以通过电源端子向管芯提供电流产生的偏移电感。

公开(公告)号：US20040022038A1

公开(公告)日：2004-02-05

申请号：US10210391

申请日：2002-07-31

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Chris Baldwin ,  Yuan-Liang Li

IPC: H05K007/06 ,  H01L023/58

CPC classification number: H01L23/642 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/183 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic package, such as an integrated circuit package, includes a cavity (310, 410 FIGS. 3, 4) on the back side of the package, which is the same side on which connectors (304, 408, FIGS. 3, 4) to a next level of interconnect are located. Within the cavity are contacts (312, 412, FIGS. 3, 4), which enable one or more discrete capacitors (302, 402, FIGS. 3, 4) to be electrically connected to the package. The package provides a very low vertical inductance path between the capacitors and an integrated circuit (314, FIG. 3) mounted on the front side of the package.

Abstract translation: 诸如集成电路封装的电子封装包括在封装的背面上的空腔（310,410，图3,4），其是连接器（304,408，图3，图4）上相同的一侧 ）到下一级互连。 在腔内是使得一个或多个分立电容器（302,402，图3，图4）能够电连接到封装件的触头（312,412，图3，图4）。 该封装在电容器和安装在封装的前侧上的集成电路（314，图3）之间提供非常低的垂直电感路径。