公开(公告)号：US20040266161A1

公开(公告)日：2004-12-30

申请号：US10753316

申请日：2004-01-09

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Ching-Fu Horng

IPC分类号： H01L021/44 ,  H01L021/4763 ,  H01L021/48

CPC分类号： H01L24/11 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/013

摘要： A method of forming a plurality of bumps over a wafer mainly comprises the steps of providing a wafer having a plurality of bonding pads, forming an adhesive layer on the surface of the wafer to cover the bonding pads, patterning the adhesive layer to expose the bonding pads to form a patterned adhesive layer, forming a barrier layer and a wetting layer on the patterned adhesive layer and the surface of the wafer, removing the barrier layer and the wetting layer not covering the patterned adhesive layer, forming a plurality of bumps on the patterned wetting layer, and reflowing the bumps.

摘要翻译： 在晶片上形成多个凸块的方法主要包括以下步骤：提供具有多个接合焊盘的晶片，在晶片的表面上形成粘合剂层以覆盖接合焊盘，图案化粘合剂层以暴露键合 衬垫以形成图案化的粘合剂层，在图案化的粘合剂层和晶片的表面上形成阻挡层和润湿层，去除不覆盖图案化的粘合剂层的阻挡层和润湿层，在其上形成多个凸块 图案化润湿层，并且回流凸块。

公开(公告)号：US20040266160A1

公开(公告)日：2004-12-30

申请号：US10709940

申请日：2004-06-08

发明人： Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

IPC分类号： H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC分类号： H01L24/13 ,  H01L23/5222 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

摘要： A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

摘要翻译： 衬底上的寄生电容防止虚拟焊料凸块结构具有至少一个形成在衬底上的导电层，用于覆盖导电层的电介质层，形成在电介质层上的凸块下金属层（UBM层）和 焊料凸块形成在UBM层上。

公开(公告)号：US20040266068A1

公开(公告)日：2004-12-30

申请号：US10731177

申请日：2003-12-09

发明人： J. Christopher Matayabas JR. ,  Constance L. Gettinger

IPC分类号： H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC分类号： H01L23/3121 ,  H01L23/3135 ,  H01L23/3737 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： The specification discloses an apparatus comprising a die mounted on a substrate, the die being connected to the substrate by a plurality of wires, and a mold cap encapsulating the die and the plurality of wires, the mold cap comprising an electrically insulating portion encapsulating the wires and at least a portion of the die and a thermally conductive portion overmolded on the die and the electrically insulating portion. Also disclosed is a process comprising providing a die connected to a substrate by a plurality of wires, encapsulating the wires and at least a portion of the die in an electrically insulating material, and encapsulating the die, the wires and the electrically insulating material in a thermally conductive material. Other embodiments are disclosed and claimed.

摘要翻译： 本说明书公开了一种装置，其包括：安装在基板上的管芯，该管芯通过多根导线与基板连接;模具盖封装该芯片和该多根金属丝，该模具盖包括电绝缘部分， 以及模具的至少一部分和在模具和电绝缘部分上包覆模制的导热部分。 还公开了一种方法，其包括通过多根导线提供连接到衬底的管芯，将电线和芯片的至少一部分封装在电绝缘材料中，并将管芯，电线和电绝缘材料封装在一个 导热材料。 公开和要求保护其他实施例。

公开(公告)号：US20040262778A1

公开(公告)日：2004-12-30

申请号：US10890684

申请日：2004-07-13

发明人： Fay Hua

IPC分类号： H01L021/48 ,  H01L023/52

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

摘要： A microelectronic package is disclosed including a microelectronic device, a substrate, and a signaling path coupling the microelectronic device with the substrate. The signaling path includes a conductive material, a solder joint, and a barrier material disposed between the conductive material and the solder joint. The barrier material may include nickel, cobalt, iron, titanium, and combinations thereof.

摘要翻译： 公开了一种微电子封装，其包括微电子器件，衬底和将微电子器件与衬底耦合的信号通路。 信号路径包括导电材料，焊接接头和设置在导电材料和焊料接头之间的阻挡材料。 阻挡材料可以包括镍，钴，铁，钛及其组合。

公开(公告)号：US20040262722A1

公开(公告)日：2004-12-30

申请号：US10863277

申请日：2004-06-09

申请人： Canon Kabushiki Kaisha

发明人： Yoshinobu Sekiguchi

IPC分类号： H01L023/48 ,  H01L021/44 ,  H01L021/48 ,  H01L021/301

CPC分类号： H01L21/6835 ,  H01L21/67132 ,  H01L21/6836 ,  H01L23/49855 ,  H01L24/81 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/75 ,  H01L2224/75314 ,  H01L2224/7565 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/10329 ,  H01L2924/14

摘要： A first adhesive member is adhered to a substrate formed with a circuit. After that, the substrate adhered with the first adhesive member is separated into a plurality of chips. Subsequently, an adhesion of a portion of the first adhesive member where desired chips are adhered is decreased, and the desired chips are selectively removed from the first adhesive member.

摘要翻译： 第一粘合剂粘附到形成有电路的基板上。 之后，用第一粘合部件粘附的基板被分离成多个芯片。 随后，减少了所需芯片粘附的第一粘合构件的一部分的粘附，并且从第一粘合构件选择性地去除期望的碎屑。

公开(公告)号：US20040253749A1

公开(公告)日：2004-12-16

申请号：US10840287

申请日：2004-05-07

发明人： Jenq-Gong Duh ,  Shui-Jin Lu

IPC分类号： H01L021/66 ,  H01L021/302 ,  H01L021/44 ,  H01L021/48

CPC分类号： H01L24/11 ,  H01L22/12 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05147 ,  H01L2224/05166

摘要： The present invention provides a method for inspecting a connecting surface of a flip chip to solve problems that the grinding, polishing and chemical etching method is used for making a sample. The present invention utilizes ion beam etching technology for making and processing a sample of the flip chip (FC). The ion beam etching technology includes two modes: keeping the energy of ion beam and increasing the etching time; and keeping the etching time and increasing the ion beam energy. The ion beam etching technology can remove a deforming portion between the solder ball and the metal pad, which is connected thereto because of the grinding and polishing. Specially, it is easy to analyse a sample of a scanning electron microscope (SEM) which includes an intermetallic compound formed between the solder ball and the metal pad connected thereto.

摘要翻译： 本发明提供了一种用于检查倒装芯片的连接表面的方法，以解决用于制造样品的研磨，抛光和化学蚀刻方法的问题。 本发明利用离子束蚀刻技术制造和处理倒装芯片（FC）的样品。 离子束蚀刻技术包括两种模式：保持离子束的能量并增加蚀刻时间; 并保持蚀刻时间并增加离子束能量。 离子束蚀刻技术可以消除由于研磨和抛光而与焊料球连接的焊球与金属焊盘之间的变形部分。 特别地，容易地分析扫描电子显微镜（SEM）的样品，其包括在焊球和与其连接的金属焊盘之间形成的金属间化合物。

公开(公告)号：US20040251561A1

公开(公告)日：2004-12-16

申请号：US10458925

申请日：2003-06-11

申请人： Fry's Metals, Inc.

发明人： Mark Wilson ,  David Garrett

IPC分类号： H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L023/29

CPC分类号： H01L21/563 ,  H01L23/293 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2924/01004 ,  H01L2924/01025 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701

摘要： A flip chip having solder bumps and an underfill that is thermoplastic and fluxing, as well as methods for making such a device. The resulting device is well suited for a simple one-step application to a printed circuit board, thereby simplifying flip chip manufacturing processes.

摘要翻译： 具有焊料凸点和热塑性和助熔剂的底部填充物的倒装芯片以及制造这种器件的方法。 所得到的器件非常适用于印刷电路板的简单的一步应用，从而简化了倒装芯片制造工艺。

公开(公告)号：US20040227256A1

公开(公告)日：2004-11-18

申请号：US10839334

申请日：2004-05-06

申请人： SHARP KABUSHIKI KAISHA

发明人： Toshiharu Seko

IPC分类号： H01L021/48 ,  H01L029/40

CPC分类号： H01L24/32 ,  H01L23/49811 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device includes a film substrate having an interconnection pattern provided on a surface thereof, a semiconductor chip mounted on the film substrate and having an electrode provided on a surface thereof, and an insulative resin portion provided between the film substrate and the semiconductor chip, the resin portion having been formed by applying an insulative resin on at least one of the film substrate and the semiconductor chip and filling a space defined between the film substrate and the semiconductor chip with the resin when the semiconductor chip is mounted on the film substrate, wherein the interconnection pattern has a projection which has a sectional shape tapered toward the electrode of the semiconductor chip and intrudes in the electrode thereby to be electrically connected to the electrode.

摘要翻译： 半导体器件包括其表面上设置有互连图案的薄膜基板，安装在薄膜基板上并具有设置在其表面上的电极的半导体芯片，以及设置在薄膜基板和半导体芯片之间的绝缘树脂部分， 所述树脂部分是通过在所述薄膜基片和所述半导体芯片中的至少一个上施加绝缘树脂而形成的，并且当所述半导体芯片安装在所述薄膜基片上时，用所述树脂填充所述薄膜基片和所述半导体芯片之间的空间， 其中所述互连图案具有突起，所述突起具有朝向所述半导体芯片的电极渐缩的截面形状并且侵入所述电极，从而与所述电极电连接。

公开(公告)号：US20040224441A1

公开(公告)日：2004-11-11

申请号：US10809515

申请日：2004-03-26

申请人： SEIKO EPSON CORPORATION

发明人： Atsushi Saito

IPC分类号： B05D005/12 ,  H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L24/11 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11332 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014

摘要： To provide a method of manufacturing an electronic part capable of reusing the remaining conductive particles and electrically connecting the electronic part to the counterpart substrate, a method of manufacturing an electronic part includes: forming a mask on an active surface of the wafer on which electrode pads of the electronic part are formed, the mask of a predetermined height having openings provided above the electrode pads, forming bumps inside of the openings of the mask provided above the electrode pads, the bumps having a height lower than that of the mask, scattering conductive particles above the active surface of the wafer, removing the conductive particles remaining on the surface of the mask, fixing the conductive particles on the surfaces of the bumps, removing the mask, and separating the electronic part from the wafer.

摘要翻译： 为了提供能够重新使用剩余的导电粒子并将电子部件电连接到对方基板的电子部件的制造方法，电子部件的制造方法包括：在晶片的有源面上形成掩模，电极焊盘 形成电子部件的掩模，其具有设置在电极焊盘上方的开口的预定高度的掩模，在电极焊盘上方形成掩模的开口内部的凸起，凸起的高度低于掩模的高度，散射导电 颗粒在晶片的有效表面之上，去除保留在掩模表面上的导电颗粒，将导电颗粒固定在凸块的表面上，去除掩模，以及将电子部件与晶片分离。

公开(公告)号：US20040224438A1

公开(公告)日：2004-11-11

申请号：US10863530

申请日：2004-06-07

申请人： International Rectifier Corporation

发明人： Martin Standing ,  Hazel Deborah Schofield

IPC分类号： H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC分类号： H01L23/492 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/81 ,  H01L24/83 ,  H01L2223/54486 ,  H01L2224/1147 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

摘要： A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

摘要翻译： 芯片级封装具有半导体MOSFET管芯，其具有覆盖有感光性液体环氧树脂层的顶部电极表面，该层被光刻图案化以暴露电极表面的部分并且用作钝化层和作为焊接掩模。 然后在钝化层上形成可焊接接触层。 单个管芯的排水侧面向下安装在金属夹子或罐中，其中漏电极设置为与罐底部延伸的凸缘共面。