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公开(公告)号：US09830284B2
公开(公告)日：2017-11-28
申请号：US14809423
申请日：2015-07-27
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G06F13/20 , G06F12/0806 , G06F12/06 , G06F12/02 , G06F3/06 , G06F13/28 , G06F13/40 , G06F15/76 , G06F15/173 , G11C7/10 , G06F12/10 , G06F12/109
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号：US09824037B2
公开(公告)日：2017-11-21
申请号：US14882824
申请日：2015-10-14
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G06F13/20 , G06F12/0806 , G06F12/06 , G06F12/02 , G06F3/06 , G06F13/28 , G06F13/40 , G06F15/76 , G06F15/173 , G11C7/10 , G06F12/10 , G06F12/109
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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3.发明申请公开(公告)号：US20150081999A1
公开(公告)日：2015-03-19
申请号：US14286055
申请日：2014-05-23
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G06F12/02
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
Abstract translation: 一般来说，本公开包括具有集成在处理器内的多个可编程单元的装置。 该装置具有将单个地址空间中的地址映射到多个可编程单元内的资源的电路，其中单个地址空间包括针对多个可编程单元中的不同可编程单元中的不同资源的地址，并且其中存在一对一 单个地址空间中的各个地址与多个可编程单元内的资源之间的对应关系。
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公开(公告)号：US20160071558A1
公开(公告)日：2016-03-10
申请号：US14882867
申请日：2015-10-14
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G11C7/10 , G06F15/173
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号：US20160070664A1
公开(公告)日：2016-03-10
申请号：US14882897
申请日：2015-10-14
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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Patent Agency Ranking
公开(公告)号：US20160034420A1
公开(公告)日：2016-02-04
申请号：US14882824
申请日：2015-10-14
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G06F15/76
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号：US20160019178A1
公开(公告)日：2016-01-21
申请号：US14809423
申请日：2015-07-27
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号：US09830285B2
公开(公告)日：2017-11-28
申请号：US14882867
申请日：2015-10-14
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G06F13/20 , G06F12/0806 , G06F12/06 , G06F12/02 , G06F3/06 , G06F13/28 , G06F13/40 , G06F15/76 , G06F15/173 , G11C7/10 , G06F12/10 , G06F12/109
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号：US09824038B2
公开(公告)日：2017-11-21
申请号：US14882897
申请日：2015-10-14
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G06F13/20 , G06F12/0806 , G06F12/06 , G06F12/02 , G06F3/06 , G06F13/28 , G06F13/40 , G06F15/76 , G06F15/173 , G11C7/10 , G06F12/10 , G06F12/109
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号：US09128818B2
公开(公告)日：2015-09-08
申请号：US14286055
申请日：2014-05-23
Applicant: Intel Corporation
Inventor： Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
Abstract translation: 一般来说，本公开包括具有集成在处理器内的多个可编程单元的装置。 该装置具有将单个地址空间中的地址映射到多个可编程单元内的资源的电路，其中单个地址空间包括针对多个可编程单元中的不同可编程单元中的不同资源的地址，并且其中存在一对一 单个地址空间中的各个地址与多个可编程单元内的资源之间的对应关系。
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