公开(公告)号：US20220085778A1

公开(公告)日：2022-03-17

申请号：US17023192

申请日：2020-09-16

Applicant: Intel Corporation

Inventor： Saurabh Anmadwar ,  Dheeraj Shetty ,  Madhuban Kishor

IPC: H03F3/45 ,  H03G5/10 ,  H03G1/00

Abstract: An active current source load of a fully differential amplifier which is converted into a transconductance (gm) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gmp at dc and becomes gmp+(gmngate+gmnsrc) at high frequency which triples the UGB when gmp=gmngate/src.

公开(公告)号：US10739729B2

公开(公告)日：2020-08-11

申请号：US16242953

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Tarun Mahajan ,  Dheeraj Shetty ,  Ramnarayanan Muthukaruppan

IPC: H03M1/50 ,  G04F10/00 ,  G05F1/56 ,  G06F1/12 ,  G06F1/06 ,  H03M1/00 ,  H03M1/12 ,  H03M1/74 ,  H03L7/089 ,  H03L7/081 ,  H03L7/10

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

公开(公告)号：US11476817B2

公开(公告)日：2022-10-18

申请号：US17023192

申请日：2020-09-16

Applicant: Intel Corporation

Inventor： Saurabh Anmadwar ,  Dheeraj Shetty ,  Madhuban Kishor

IPC: H03F3/45 ,  H03G1/00 ,  H03G5/10

Abstract: An active current source load of a fully differential amplifier which is converted into a transconductance (gm) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gmp at dc and becomes gmp+(gmngate+gmnsrc) at high frequency which triples the UGB when gmp=gmngate/src.

公开(公告)号：US10175655B2

公开(公告)日：2019-01-08

申请号：US15462732

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Tarun Mahajan ,  Dheeraj Shetty ,  Ramnarayanan Muthukaruppan

IPC: H03M1/50 ,  G04F10/00 ,  G05F1/56 ,  G06F1/06 ,  H03M1/00 ,  H03M1/12

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.