公开(公告)号：US20230102991A1

公开(公告)日：2023-03-30

申请号：US17484542

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Edward Brazil ,  Bryan J. Gran ,  Ohad Itzhaki

IPC: G06F11/22 ,  G06F11/273 ,  G06F11/263

Abstract: Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

公开(公告)号：US20200096569A1

公开(公告)日：2020-03-26

申请号：US16142591

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Larisa Novakovsky ,  Edward Brazil ,  Alexander Gendler

IPC: G01R31/3185 ,  G06F1/32 ,  G01R31/319

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

公开(公告)号：US10775434B2

公开(公告)日：2020-09-15

申请号：US16142591

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Larisa Novakovsky ,  Edward Brazil ,  Alexander Gendler

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/3203 ,  G06F11/27

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

公开(公告)号：US10727836B1

公开(公告)日：2020-07-28

申请号：US16404616

申请日：2019-05-06

Applicant: Intel Corporation

Inventor： Eashwar Raghuraman ,  Satish Sethuraman ,  Edward Brazil

IPC: H03K19/173 ,  H03K17/693

Abstract: A tristate and pass-gate based multiplexer circuit structure is described with full scan coverage capability. The circuit provides deterministic state at its output avoiding high impedance (Z) logic states in silicon. This is realized using a pull-up transistors, pull-down transistors, or through stages of combinational logic combining the multiplexer selects/enables feeding a pull-up or pull-down transistors.