公开(公告)号：US20240214177A1

公开(公告)日：2024-06-27

申请号：US18145024

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel GRUBER ,  Edwin THALLER ,  Michael KALCHER

IPC: H04L7/033 ,  G06F1/10 ,  G06F1/12 ,  H03L7/081

CPC classification number: H04L7/0337 ,  G06F1/10 ,  G06F1/12 ,  H03L7/0812

Abstract: A multi-device system and a method for phase alignment of multiple devices in a multi-device system. The system includes a plurality of devices, a plurality of clock dividers, and a delay circuit. The plurality of devices are configured to operate based on a first clock signal. The clock dividers are configured to generate a second clock signal from the first clock signal and provide the second clock signal to the devices. The delay circuit is configured to incur a specific delay to the second clock signal provided to the devices such that a phase of the second clock signal provided to the devices is spread over time. Each of the clock dividers may be reset based on a reference clock signal provided to each clock divider, and the delay circuit may incur the specific delay on the reference clock signal provided to each clock divider.

公开(公告)号：US20240213989A1

公开(公告)日：2024-06-27

申请号：US18145867

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Marc Jan Georges TIEBOUT ,  Edwin THALLER ,  Kameran AZADET

IPC: H03L7/091 ,  H03L7/07 ,  H03L7/099

CPC classification number: H03L7/091 ,  H03L7/07 ,  H03L7/0991

Abstract: A system and method for testing or determining a phase noise and/or jitter of a phase locked loop (PLL). The system includes a first PLL configured to generate a first clock signal based on a reference clock signal, a first buffer for providing the reference clock signal to the first PLL, a mixer configured to mix the first clock signal with a second clock signal, an analog-to-digital converter (ADC) configured to convert an output of the mixer to digital data, and a processing circuit configured to process the digital data to determine a phase noise or jitter of the first PLL and generate an output indicative of the phase noise or jitter of the first PLL. The system may include a second PLL configured to generate the second clock signal based on the reference clock signal, and a second buffer for providing the reference clock signal to the second PLL.