公开(公告)号：US20240214177A1

公开(公告)日：2024-06-27

申请号：US18145024

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel GRUBER ,  Edwin THALLER ,  Michael KALCHER

IPC: H04L7/033 ,  G06F1/10 ,  G06F1/12 ,  H03L7/081

CPC classification number: H04L7/0337 ,  G06F1/10 ,  G06F1/12 ,  H03L7/0812

Abstract: A multi-device system and a method for phase alignment of multiple devices in a multi-device system. The system includes a plurality of devices, a plurality of clock dividers, and a delay circuit. The plurality of devices are configured to operate based on a first clock signal. The clock dividers are configured to generate a second clock signal from the first clock signal and provide the second clock signal to the devices. The delay circuit is configured to incur a specific delay to the second clock signal provided to the devices such that a phase of the second clock signal provided to the devices is spread over time. Each of the clock dividers may be reset based on a reference clock signal provided to each clock divider, and the delay circuit may incur the specific delay on the reference clock signal provided to each clock divider.

公开(公告)号：US20220416806A1

公开(公告)日：2022-12-29

申请号：US17358152

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Michael KALCHER ,  Daniel GRUBER ,  Martin CLARA

IPC: H03M1/80

Abstract: Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.

公开(公告)号：US20230198533A1

公开(公告)日：2023-06-22

申请号：US17645462

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Daniel GRUBER ,  Michael KALCHER ,  Alessandra CANGIANIELLO

IPC: H03M1/00 ,  H03M1/06

CPC classification number: H03M1/002 ,  H03M1/0682

Abstract: A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.

公开(公告)号：US20240223198A1

公开(公告)日：2024-07-04

申请号：US18147717

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Daniel GRUBER ,  Michael KALCHER ,  Martin CLARA

IPC: H03M1/10

CPC classification number: H03M1/10

Abstract: A segmented digital-to-analog converter (DAC). The segmented DAC includes at least two DAC segments. The DAC includes at least one overrange DAC configured to generate a dither subtraction signal based on an overrange DAC control data, and a dither control circuit configured to add a dither to the input data for the segmented DAC and generate the overrange DAC control data to compensate the dither. The dither subtraction signal is combined with the output signals of the DAC segments in an analog domain. The DAC includes a segment mismatch correction circuit configured to modify the input data for the segmented DAC or input data for at least one segment to correct a mismatch error of one or more of the segments and/or the at least one overrange DAC.

公开(公告)号：US20240213992A1

公开(公告)日：2024-06-27

申请号：US18145025

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel GRUBER ,  Michael KALCHER ,  Martin CLARA

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: A digital-to-analog converter (DAC) and a method for correcting amplitude and/or skew error in a DAC. The DAC includes a main DAC, cell error determination circuit, a correction DAC, and a combiner. The main DAC includes a plurality of DAC cells. The cell error determination circuit is configured to determine an amplitude error and/or a skew error of each of the plurality of DAC cells and generate error data of the DAC based on the input data to the DAC cells. The correction DAC is configured to generate an error signal based on the error data. The combiner is configured to combine the error signal with an output of the main DAC.

公开(公告)号：US20220209786A1

公开(公告)日：2022-06-30

申请号：US17132000

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Daniel GRUBER ,  Michael KALCHER ,  Martin CLARA

IPC: H03M1/72 ,  H04B1/04 ,  H04W88/08

Abstract: A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by ri bit positions for the i-th second digital control code, wherein ri is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.

公开(公告)号：US20220103142A1

公开(公告)日：2022-03-31

申请号：US17426065

申请日：2019-10-10

Applicant: INTEL CORPORATION

Inventor： Daniel GRUBER ,  Michael KALCHER

IPC: H03F3/50 ,  G05F1/575 ,  G05F1/618 ,  H03F3/45

Abstract: Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (Mp) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (Mc) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−gmf) comprising an input terminal and an output terminal. The first terminal of the first transistor (Mp) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (Mp) is coupled with the first terminal of the second transistor (Mc) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−gmf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−gmf).