公开(公告)号：US11545441B2

公开(公告)日：2023-01-03

申请号：US17102726

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Vipul Vijay Mehta ,  Eric Jin Li ,  Sanka Ganesan ,  Debendra Mallik ,  Robert Leon Sankman

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/14 ,  H01L21/768

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

公开(公告)号：US20170287851A1

公开(公告)日：2017-10-05

申请号：US15607270

申请日：2017-05-26

Applicant: Intel Corporation

Inventor： Anna M. Prakash ,  Reynaldo Alberto Olmedo ,  Venmathy McMahan ,  Rajendra C. Dias ,  Joshua David Heppner ,  Ann Jinyan Xu ,  Sriya Sanyal ,  Eric Jin Li

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/56 ,  H01L23/293 ,  H01L23/295 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.

公开(公告)号：US09685413B1

公开(公告)日：2017-06-20

申请号：US15089328

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Anna M. Prakash ,  Reynaldo Alberto Olmedo ,  Venmathy McMahan ,  Rajendra C. Dias ,  Joshua David Heppner ,  Ann Jinyan Xu ,  Sriya Sanyal ,  Eric Jin Li

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/56 ,  H01L23/293 ,  H01L23/295 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.

公开(公告)号：US10910317B2

公开(公告)日：2021-02-02

申请号：US16461316

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Vipul Vijay Mehta ,  Eric Jin Li ,  Sanka Ganesan ,  Debendra Mallik ,  Robert Leon Sankman

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/14 ,  H01L21/768

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

公开(公告)号：US09991211B2

公开(公告)日：2018-06-05

申请号：US15607270

申请日：2017-05-26

Applicant: Intel Corporation

Inventor： Anna M. Prakash ,  Reynaldo Alberto Olmedo ,  Venmathy McMahan ,  Rajendra C. Dias ,  Joshua David Heppner ,  Ann Jinyan Xu ,  Sriya Sanyal ,  Eric Jin Li

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/56 ,  H01L23/293 ,  H01L23/295 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.