公开(公告)号：US12209975B2

公开(公告)日：2025-01-28

申请号：US17883678

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： John Ferdinand Magana ,  Guojing Zhang

IPC: G01N21/958

Abstract: The present disclosure is directed to a reticle assembly having a reticle and a pellicle attached to a pellicle support frame positioned on the reticle and includes a sensor assembly having optical and sensor components, which monitor the pellicle. The optical components and the sensor components of the sensor assembly may be coupled to a controller, which may be further coupled to one or more semiconductor process tools.

公开(公告)号：US11604406B2

公开(公告)日：2023-03-14

申请号：US16521445

申请日：2019-07-24

Applicant: Intel Corporation

Inventor： John Magana ,  Guojing Zhang ,  Yang Cao

IPC: G03F1/24

Abstract: Embodiments disclosed herein include EUV reticles and methods of forming such reticles. In an embodiment a method of forming an EUV reticle comprises providing a reticle, where the reticle comprises, a substrate, a mirror layer over the substrate, where the mirror layer comprises a plurality of first mirror layers and second mirror layers in an alternating pattern, and a capping layer over the mirror layer. In an embodiment, the method may further comprise disposing a first layer over the capping layer, patterning an opening in the first layer, and disposing a second layer in the opening, where the second layer is disposed with an electroless deposition process.

公开(公告)号：US11300885B2

公开(公告)日：2022-04-12

申请号：US16045253

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Robert Bristol ,  Guojing Zhang ,  Tristan Tronic ,  John Magana ,  Chang Ju Choi ,  Arvind Sundaramurthy ,  Richard Schenker

IPC: G03F7/20 ,  G03F1/24

Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.

公开(公告)号：US20220075259A1

公开(公告)日：2022-03-10

申请号：US17530755

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： John Magana ,  Guojing Zhang

IPC: G03F1/64

Abstract: Monolithic framed pellicle membrane integrating a structural framing member with a membrane spanning the framing member. The monolithic frame pellicle membrane is suitable as an overlay of a reticle employed in lithography operations of integrated circuit manufacture. A semiconductor-on-insulator (SOI) wafer may be machined from the backside, for example with a bonnet polisher, to form a pellicle framing member by removing a portion of a base semiconductor substrate of the SOI wafer selectively to top semiconductor layer of the SOI wafer, which is retained as a pellicle membrane. In some exemplary embodiments suitable for extreme ultraviolet (EUV) lithography applications, at least the top semiconductor layer of the SOI wafer is a substantially monocrystalline silicon layer.

公开(公告)号：US11561466B2

公开(公告)日：2023-01-24

申请号：US17530755

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： John Magana ,  Guojing Zhang

IPC: G03F1/64

Abstract: Monolithic framed pellicle membrane integrating a structural framing member with a membrane spanning the framing member. The monolithic frame pellicle membrane is suitable as an overlay of a reticle employed in lithography operations of integrated circuit manufacture. A semiconductor-on-insulator (SOI) wafer may be machined from the backside, for example with a bonnet polisher, to form a pellicle framing member by removing a portion of a base semiconductor substrate of the SOI wafer selectively to top semiconductor layer of the SOI wafer, which is retained as a pellicle membrane. In some exemplary embodiments suitable for extreme ultraviolet (EUV) lithography applications, at least the top semiconductor layer of the SOI wafer is a substantially monocrystalline silicon layer.

公开(公告)号：US11194246B1

公开(公告)日：2021-12-07

申请号：US16832456

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： John Magana ,  Guojing Zhang

IPC: G03F1/64

Abstract: Monolithic framed pellicle membrane integrating a structural framing member with a membrane spanning the framing member. The monolithic frame pellicle membrane is suitable as an overlay of a reticle employed in lithography operations of integrated circuit manufacture. A semiconductor-on-insulator (SOI) wafer may be machined from the backside, for example with a bonnet polisher, to form a pellicle framing member by removing a portion of a base semiconductor substrate of the SOI wafer selectively to top semiconductor layer of the SOI wafer, which is retained as a pellicle membrane. In some exemplary embodiments suitable for extreme ultraviolet (EUV) lithography applications, at least the top semiconductor layer of the SOI wafer is a substantially monocrystalline silicon layer.