公开(公告)号：US11715790B2

公开(公告)日：2023-08-01

申请号：US16390819

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Yang Cao ,  Han Wui Then ,  Johann Christian Rode ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Paul B. Fischer

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/49 ,  H01L29/45 ,  H01L21/02 ,  H01L29/808 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02458 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/49 ,  H01L29/4925 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/808 ,  H01L29/1066

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

公开(公告)号：US11195798B2

公开(公告)日：2021-12-07

申请号：US15300569

申请日：2014-07-25

Applicant: Intel Corporation

Inventor： Yang Cao ,  Akm Shaestagir Chowdhury ,  Jeff Grunes

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/532

Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

公开(公告)号：US11604406B2

公开(公告)日：2023-03-14

申请号：US16521445

申请日：2019-07-24

Applicant: Intel Corporation

Inventor： John Magana ,  Guojing Zhang ,  Yang Cao

IPC: G03F1/24

Abstract: Embodiments disclosed herein include EUV reticles and methods of forming such reticles. In an embodiment a method of forming an EUV reticle comprises providing a reticle, where the reticle comprises, a substrate, a mirror layer over the substrate, where the mirror layer comprises a plurality of first mirror layers and second mirror layers in an alternating pattern, and a capping layer over the mirror layer. In an embodiment, the method may further comprise disposing a first layer over the capping layer, patterning an opening in the first layer, and disposing a second layer in the opening, where the second layer is disposed with an electroless deposition process.

公开(公告)号：US12080648B2

公开(公告)日：2024-09-03

申请号：US17517472

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Yang Cao ,  Akm Shaestagir Chowdhury ,  Jeff Grunes

IPC: H01L23/532 ,  H01L21/288 ,  H01L21/768

CPC classification number: H01L23/53261 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

公开(公告)号：US11973143B2

公开(公告)日：2024-04-30

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Benjamin Chu-Kung ,  Subrina Rafique ,  Devin Merrill ,  Ashish Agrawal ,  Harold Kennel ,  Yang Cao ,  Dipanjan Basu ,  Jessica Torres ,  Anand Murthy

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20200335590A1

公开(公告)日：2020-10-22

申请号：US16390819

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Yang Cao ,  Han Wui Then ,  Johann Christian Rode ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Paul B. Fischer

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.