公开(公告)号：US20190043580A1

公开(公告)日：2019-02-07

申请号：US16143033

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Agostino PIROVANO ,  Hernan A. CASTRO ,  Innocenzo TORTORELLI ,  Andrea REDAELLI

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/73 ,  G11C2213/77 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/141

Abstract: Reset refresh techniques are described, which can enable reducing or canceling the drift of threshold voltage distributions exhibited by memory cells. In one example a memory device includes an array of memory cells. The memory cells include a chalcogenide storage material. The memory device includes hardware logic to program the memory cells, including logic to detect whether a memory cell is selectable with a first voltage having a first polarity. In response to detection that a memory cell is not selectable with the first voltage, the memory cell is refreshed the memory cell with a second voltage that has a polarity opposite to the first voltage. After the refresh with the second voltage, the memory cell can be programmed with the first voltage having the first polarity.

公开(公告)号：US20170330621A1

公开(公告)日：2017-11-16

申请号：US15633454

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Hernan A. CASTRO

IPC: G11C13/00 ,  G11C13/02 ,  G11C7/10 ,  G11C7/12 ,  G11C16/06

CPC classification number: G11C13/0097 ,  G11C7/10 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/02 ,  G11C16/06

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US20180330789A1

公开(公告)日：2018-11-15

申请号：US15983746

申请日：2018-05-18

Applicant: Intel Corporation

Inventor： Hernan A. CASTRO

IPC: G11C13/00 ,  G11C13/02 ,  G11C7/10 ,  G11C16/06 ,  G11C7/12

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.