公开(公告)号：US10079158B2

公开(公告)日：2018-09-18

申请号：US14569438

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jackson Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Kuan-Yu Chen

IPC: H05K7/00 ,  H01P3/08 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H05K1/00 ,  H05K1/11 ,  H01P3/00 ,  H01P3/02 ,  H01P5/02 ,  H05K1/02 ,  H01P3/04

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/10 ,  H01P3/003 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P3/082 ,  H01P5/028 ,  H05K1/0224 ,  H05K1/0242 ,  H05K1/0245 ,  H05K3/462 ,  H05K3/4638 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/1189

Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

公开(公告)号：US20160174374A1

公开(公告)日：2016-06-16

申请号：US14569438

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jackson Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Kuan-Yu Chen

IPC: H05K1/11 ,  H01L21/48 ,  H05K3/40 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/10 ,  H01P3/003 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P3/082 ,  H01P5/028 ,  H05K1/0224 ,  H05K1/0242 ,  H05K1/0245 ,  H05K3/462 ,  H05K3/4638 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/1189

Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

Abstract translation: 公开了一种在衬底中包括垂直沟槽布线的互连拓扑。 在一个实施例中，互连包括具有包括第一接地平面层的多个层的衬底; 形成差分信号对的一对信号导体，所述一对信号导体中的每个导体具有第一部分和第二部分，所述第二部分从所述第一部分延伸到所述多个层中的至少一个层中，其中， 第二部分小于第一部分的宽度; 并且其中所述第一接地层仅为第一部分层，并且具有比所述第一部分层更靠近所述一对信号导体的第一空隙区域。