公开(公告)号：US20250020874A1

公开(公告)日：2025-01-16

申请号：US18902427

申请日：2024-09-30

Applicant: Intel Corporation

Inventor： Todd R. COONS ,  Michael RUTIGLIANO ,  Joe F. WALCZYK ,  Abram M. DETOFSKY

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34 ,  H01L23/367 ,  H01L25/075 ,  H01L33/58 ,  H01L33/62 ,  H04B10/40

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.

公开(公告)号：US20220196732A1

公开(公告)日：2022-06-23

申请号：US17131604

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Todd R. COONS ,  Michael RUTIGLIANO ,  Joe F. WALCZYK ,  Abram M. DETOFSKY

IPC: G01R31/308 ,  G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical plugs used to cover optical connectors of a photonics package to protect the connectors. The active optical plugs may also be used to perform testing of the photonics package, including generating light to be sent to the photonics package and to detect light received from the photonics package as part of the test protocol. This allows testing the optical connection and the photonics package, without exposing the optical connections of the package to damage from dust or physical contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20220200183A1

公开(公告)日：2022-06-23

申请号：US17132921

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Srikant NEKKANTY ,  Debendra MALLIK ,  Joe F. WALCZYK ,  Saikumar JAYARAMAN ,  Feroz MOHAMMAD

IPC: H01R13/11 ,  H01R12/58 ,  H01L25/075 ,  H01L23/00 ,  H01L23/532

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

公开(公告)号：US20220196924A1

公开(公告)日：2022-06-23

申请号：US17131630

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Joe F. WALCZYK ,  Todd R. COONS ,  Michael RUTIGLIANO ,  Abram M. DETOFSKY

IPC: G02B6/38

Abstract: A photonic connector comprises a first ferrule having a first plurality of optical fibers. A membrane cover is attached to the first ferrule and covers ends of the first plurality of optical fibers. Once the first ferrule is mated with a second ferrule having a second plurality of optical fibers, the membrane cover is pierced by the first plurality of optical fibers, the second plurality of optical fibers, or both.

公开(公告)号：US20220196915A1

公开(公告)日：2022-06-23

申请号：US17132912

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Todd R. COONS ,  Michael RUTIGLIANO ,  Joe F. WALCZYK ,  Abram M. DETOFSKY

IPC: G02B6/12 ,  H01L33/62 ,  H01L33/58 ,  H04B10/40 ,  H01L25/075

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.

公开(公告)号：US20210305196A1

公开(公告)日：2021-09-30

申请号：US16828651

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Morten JENSEN ,  Michael RYAN ,  Srikant NEKKANTY ,  Joe F. WALCZYK

IPC: H01L23/00 ,  H01R13/24 ,  H01R12/71

Abstract: An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector.