公开(公告)号：US20220116206A1

公开(公告)日：2022-04-14

申请号：US17558627

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： David KEHLET ,  Shuanghong SUN ,  Saikumar JAYARAMAN ,  Fariaz KARIM

IPC: H04L9/08 ,  H04L9/32 ,  G06F7/58

Abstract: A first semiconductor device includes a processor configured to generate a random number at initial test of a second semiconductor device after fabrication of the second semiconductor device in a supply chain related to the second semiconductor device, and send the generated random number to the second semiconductor device. The processor is further configured to receive a first signature that is signed over the sent random number by the second semiconductor device using a first private key that is stored in the second semiconductor device, among a first private and public key pair, and test the received first signature, using a first public key that is stored in the first semiconductor device, among the first private and public key pair, to determine whether the second semiconductor device is authenticated.

公开(公告)号：US20200043894A1

公开(公告)日：2020-02-06

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George VAKANAS ,  Aastha UPPAL ,  Shereen ELHALAWATY ,  Aaron MCCANN ,  Edvin CETEGEN ,  Tannaz HARIRCHIAN ,  Saikumar JAYARAMAN

IPC: H01L25/065 ,  H01L27/108 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

公开(公告)号：US20240054502A1

公开(公告)日：2024-02-15

申请号：US17883718

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Michael A. SCHROEDER ,  Sean BUSHELL ,  William F. HERRINGTON ,  Hannah ROWE ,  Sarah SHAHRAINI ,  Ryan PATE ,  Erasenthiran POONJOLAI ,  Saikumar JAYARAMAN ,  Fariaz KARIM

IPC: G06Q30/00 ,  G06V20/00 ,  G06V20/80 ,  G06V10/14 ,  H04L9/32

CPC classification number: G06Q30/018 ,  G06V20/95 ,  G06V20/80 ,  G06V10/14 ,  H04L9/3236

Abstract: The present disclosure is directed to an authentication system, tools, and methods for authentication including a first inspection tool that generates first images for a first inspection of a device, and a first processor for processing the first images using a hashing algorithm, for which the first inspection tool and the first processor are sited at a first location, and a second inspection tool that generates second images for a second inspection of the device, and a second processor for processing the second images using the hashing algorithm, for which the second inspection tool and the second processor are sited at a second location. The second processor compares the first and second sets of hash values to authenticate the device as being authentic and untampered.

公开(公告)号：US20220200183A1

公开(公告)日：2022-06-23

申请号：US17132921

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Srikant NEKKANTY ,  Debendra MALLIK ,  Joe F. WALCZYK ,  Saikumar JAYARAMAN ,  Feroz MOHAMMAD

IPC: H01R13/11 ,  H01R12/58 ,  H01L25/075 ,  H01L23/00 ,  H01L23/532

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

公开(公告)号：US20180182697A1

公开(公告)日：2018-06-28

申请号：US15900743

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Daewoong SUH ,  Saikumar JAYARAMAN

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H01L23/00 ,  H01L21/56 ,  H05K3/30

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/305 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/043 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.

公开(公告)号：US20170033069A1

公开(公告)日：2017-02-02

申请号：US15295952

申请日：2016-10-17

Applicant: Intel Corporation

Inventor： Mihir A. Oka ,  Edward R. PRACK ,  Dingying XU ,  Saikumar JAYARAMAN

IPC: H01L23/00 ,  C09D5/20 ,  C09D7/12 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L24/11 ,  C08G73/22 ,  C09D5/20 ,  C09D7/63 ,  C09D179/04 ,  C09D179/08 ,  C09D181/04 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31127 ,  H01L24/13 ,  H01L2224/05568 ,  H01L2224/11009 ,  H01L2224/11332 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2924/095 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00 ,  C08L83/04

Abstract: Techniques are disclosed for protecting a surface using a dry-removable protective coating that does not require chemical solutions to be removed. In an embodiment, a protective layer is disposed on a surface. The protective layer is composed of one layer that adheres to the surface. The surface is then processed while the protective coating is on the surface. Thereafter, the protective layer is removed from the surface by separating the protective layer away from the surface without the use of chemical solutions.

Abstract translation: 公开了用于使用不需要除去化学溶液的可干燥去除的保护涂层来保护表面的技术。 在一个实施例中，保护层设置在表面上。 保护层由附着在表面上的一层组成。 然后在表面上保护表面进行处理。 此后，通过将保护层从表面分离而不使用化学溶液，从表面除去保护层。