公开(公告)号：US20210307153A1

公开(公告)日：2021-09-30

申请号：US16828447

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Feroz MOHAMMAD ,  Ralph V. MIELE ,  Thomas BOYD ,  Steven A. KLEIN ,  Gregorio R. MURTAGIAN ,  Eric W. BUDDRIUS ,  Daniel NEUMANN ,  Rolf LAIDO

IPC: H05K1/02 ,  H01R12/85 ,  H05K1/18

Abstract: Embodiments disclosed herein include assemblies. In an embodiment, an assembly comprises a socket and a bolster plate on a board, where the bolster plate has load studs and an opening that surrounds the socket; a shim having first and second ends; and a carrier on the bolster plate, where the carrier has an opening and cutouts. The shim may have an opening through the first end as the second end is affixed to the carrier. The opening of the shim entirely over one cutout from a corner region of the carrier. In an embodiment, the assembly comprises an electronic package in the opening of the carrier, where the electronic package is affixed to the carrier, and a heatsink over the electronic package and carrier, where the first end is directly coupled to a surface of the heatsink and a surface of one load stud of the bolster plate.

公开(公告)号：US20220200183A1

公开(公告)日：2022-06-23

申请号：US17132921

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Srikant NEKKANTY ,  Debendra MALLIK ,  Joe F. WALCZYK ,  Saikumar JAYARAMAN ,  Feroz MOHAMMAD

IPC: H01R13/11 ,  H01R12/58 ,  H01L25/075 ,  H01L23/00 ,  H01L23/532

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

公开(公告)号：US20210305731A1

公开(公告)日：2021-09-30

申请号：US16833221

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Steven A. KLEIN ,  Kuang LIU ,  Srikant NEKKANTY ,  Feroz MOHAMMAD ,  Donald Tiendung TRAN ,  Srinivasa ARAVAMUDHAN ,  Hemant Mahesh SHAH ,  Alexander W. HUETTIS

IPC: H01R12/70 ,  H01R43/04

Abstract: Systems, apparatus, and/or processes directed to applying pressure to a socket to alter a shape of the socket to improve a connection between the socket and a substrate, printed circuit board, or other component. The socket may receive one or more chips, may be an interconnect, or may be some other structure that is part of a package. The shape of the socket may be flattened so that a side of the socket may form a high-quality physical and electrical coupling with the substrate.

公开(公告)号：US20200381388A1

公开(公告)日：2020-12-03

申请号：US16424227

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Feroz MOHAMMAD ,  Srinivasa R. ARAVAMUDHAN

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/34

Abstract: Embodiments herein relate to systems, apparatuses, or processes for coupling or decoupling two substrates by heating pins on one of the substrates and either inserting or withdrawing the heated pins from solder elements on a BGA. In particular, by heating a plurality of pins on a first side of a first substrate, where the plurality of pins are substantially perpendicular to a plane of the substrate, inserting the heated plurality of pins into BGA attached to a second substrate where the BGA includes a plurality of solder elements aligned with the plurality of pins and where the heated plurality of pins melt the plurality of solder elements upon insertion. The inserted plurality of pins physically and/or electrically couple the first substrate and the second substrate.