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    Instruction and Logic for Support of Code Modification
    3.
    发明申请
    Instruction and Logic for Support of Code Modification 有权

    公开(公告)号：US20170242705A1

    公开(公告)日：2017-08-24

    申请号：US15589445

    申请日：2017-05-08

    申请人： Intel Corporation

    发明人： John H. Kelm ,  David P. Keppel ,  David N. Mackintosh

    IPC分类号： G06F9/30 ,  G06F12/0875

    CPC分类号： G06F9/30174 ,  G06F9/4552 ,  G06F12/0875 ,  G06F2212/452

    摘要： A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.

    Instruction and logic for support of code modification
    4.
    发明授权
    Instruction and logic for support of code modification 有权

    公开(公告)号：US09971599B2

    公开(公告)日：2018-05-15

    申请号：US15589445

    申请日：2017-05-08

    申请人： Intel Corporation

    发明人： John H. Kelm ,  David P. Keppel ,  David N. Mackintosh

    IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F12/0875

    CPC分类号： G06F9/30174 ,  G06F9/4552 ,  G06F12/0875 ,  G06F2212/452

    摘要： A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.

    Managing dynamic capacitance using code scheduling
    7.
    发明授权
    Managing dynamic capacitance using code scheduling 有权

    公开(公告)号：US10108454B2

    公开(公告)日：2018-10-23

    申请号：US14221750

    申请日：2014-03-21

    申请人： Intel Corporation

    发明人： Vjekoslav Svilan ,  David N. Mackintosh

    IPC分类号： G06F9/48 ,  G06F1/32 ,  G06F8/41

    摘要： In an embodiment, a processor includes a schedule logic to schedule a set of instructions for execution in an execution logic of the processor and a power analysis logic having a first calculation logic to calculate a maximum dynamic capacitance for at least a portion of the processor and a second calculation logic to calculate a dynamic capacitance estimate for execution of the set of instructions. A rescheduling of the set of instructions may occur based on a comparison of the dynamic capacitance estimate and the maximum dynamic capacitance. Other embodiments are described and claimed.

    APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION
    10.
    发明申请
    APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION 审中-公开
    选择和方法选择执行委托指令

    公开(公告)号：US20160283247A1

    公开(公告)日：2016-09-29

    申请号：US14668605

    申请日：2015-03-25

    申请人： Intel Corporation

    发明人： Girish Venkatasubramanian ,  Ethan Schuchman ,  David Keppel ,  Sebastian Winkel ,  David N. Mackintosh ,  Jaroslaw Topp

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30087 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/455 ,  G06F9/45516 ,  G06F9/4552

    摘要： Methods and apparatuses relating to selectively executing a commit instruction. In one embodiment, a data storage device stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction to be executed by the hardware processor, marking a commit instruction one of for execution and for optional execution by the hardware processor, and including a hint for a commit instruction marked for optional execution; and a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.

    摘要翻译： 与选择性地执行提交指令有关的方法和装置。 在一个实施例中，数据存储装置存储当硬件处理器执行时硬件处理器执行以下操作的代码：将指令转换成由硬件处理器执行的转换指令，标记提交指令以执行和 用于硬件处理器的可选执行，并且包括用于可选执行标记的提交指令的提示; 以及硬件提交单元，用于基于提示来确定标记为可选执行的提交指令是否被执行。