公开(公告)号：US11663154B2

公开(公告)日：2023-05-30

申请号：US17721413

申请日：2022-04-15

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4031 ,  G06F13/1652 ,  G06F13/387 ,  G06F13/4208 ,  G06F13/4265

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US12001353B2

公开(公告)日：2024-06-04

申请号：US17819390

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1652 ,  G06F13/4022 ,  G06F13/4269

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

公开(公告)号：US11442876B2

公开(公告)日：2022-09-13

申请号：US16426361

申请日：2019-05-30

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

公开(公告)号：US10776302B2

公开(公告)日：2020-09-15

申请号：US16373472

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US20230026906A1

公开(公告)日：2023-01-26

申请号：US17819390

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

公开(公告)号：US20220350769A1

公开(公告)日：2022-11-03

申请号：US17721413

申请日：2022-04-15

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US11308018B2

公开(公告)日：2022-04-19

申请号：US17015963

申请日：2020-09-09

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US20190227972A1

公开(公告)日：2019-07-25

申请号：US16373472

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.