公开(公告)号：US12057386B2

公开(公告)日：2024-08-06

申请号：US17024507

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Wei Qian ,  Cung Tran ,  Sungbong Park ,  John Heck ,  Mark Isenberger ,  Seth Slavin ,  Mengyuan Huang ,  Kelly Magruder ,  Harel Frish ,  Reece Defrees ,  Zhi Li

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L23/528

Abstract: Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.

公开(公告)号：US20240184048A1

公开(公告)日：2024-06-06

申请号：US18496672

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Harel Frish ,  Pegah Seddighian ,  Kelly Magruder ,  Olufemi Dosunmu

IPC: G02B6/14 ,  G02B6/122

CPC classification number: G02B6/14 ,  G02B6/1228 ,  G02B2006/12152

Abstract: Embodiments relate to an apparatus that includes: an input stage with an input Si slab height, an input Si waveguide height, and an input height difference between the input Si slab height and the input Si waveguide height; an output stage with an output Si slab height that is different from the input Si slab height, an output Si waveguide height that is different from the input Si waveguide height, and an output height difference between the output Si slab height and the output Si waveguide height that is different from the input height difference; and a transition stage positioned between the input stage and the output stage, wherein the transition stage has a transition Si slab height, a transition Si waveguide height, and a transition height difference between the transition Si slab height and the transition Si waveguide height. Other embodiments may be described and/or claimed.

公开(公告)号：US20220416097A1

公开(公告)日：2022-12-29

申请号：US17358921

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： David Kohen ,  Kelly Magruder ,  Parastou Fakhimi ,  Zhi Li ,  Cung Tran ,  Wei Qian ,  Mark Isenberger ,  Mengyuan Huang ,  Harel Frish ,  Reece DeFrees ,  Ansheng Liu

IPC: H01L31/0232 ,  G02B6/12 ,  H01L31/105 ,  H01L31/107 ,  H01L31/18

Abstract: A photodetector structure over a partial length of a silicon waveguide structure within a photonic integrated circuit (PIC) chip. The photodetector structure is embedded within a cladding material surrounding the waveguide structure. The photodetector structure includes an absorption region, for example comprising Ge. A sidewall of the cladding material may be lined with a sacrificial spacer. After forming the absorption region, the sacrificial spacer may be removed and passivation material formed over a sidewall of the absorption region. Between the absorption region an impurity-doped portion of the waveguide structure there may be a carrier multiplication region, for example comprising crystalline silicon. If present, edge facets of the carrier multiplication region may be protected by a spacer material during the formation of an impurity-doped charge carrier layer. Occurrence of edge facets may be mitigated by embedding a portion of the photodetector structure with a thickness of the waveguide structure.