公开(公告)号：US12230714B2

公开(公告)日：2025-02-18

申请号：US18622615

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Ritesh K. Das ,  Kiran Chikkadi ,  Ryan Pearce

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/02

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US11705453B2

公开(公告)日：2023-07-18

申请号：US16294380

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Kiran Chikkadi

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/768 ,  H01L21/308 ,  H01L23/00

CPC classification number: H01L27/0924 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.

公开(公告)号：US12224349B2

公开(公告)日：2025-02-11

申请号：US16868828

申请日：2020-05-07

Applicant: Intel Corporation

Inventor： Ritesh K. Das ,  Kiran Chikkadi ,  Ryan Pearce

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/02

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US11869889B2

公开(公告)日：2024-01-09

申请号：US16579055

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Scott B. Clendenning ,  Jessica Torres ,  Lukas Baumgartel ,  Kiran Chikkadi ,  Diane Lancaster ,  Matthew V. Metz ,  Florian Gstrein ,  Martin M. Mitan ,  Rami Hourani

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/538 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5384 ,  H01L23/5389 ,  H01L27/0924 ,  H01L21/823462 ,  H01L21/823871

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.