公开(公告)号：US11869889B2

公开(公告)日：2024-01-09

申请号：US16579055

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Scott B. Clendenning ,  Jessica Torres ,  Lukas Baumgartel ,  Kiran Chikkadi ,  Diane Lancaster ,  Matthew V. Metz ,  Florian Gstrein ,  Martin M. Mitan ,  Rami Hourani

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/538 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5384 ,  H01L23/5389 ,  H01L27/0924 ,  H01L21/823462 ,  H01L21/823871

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US12051698B2

公开(公告)日：2024-07-30

申请号：US17030350

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Daniel G. Ouellette ,  Daniel B. O'Brien ,  Jeffrey S. Leib ,  Orb Acton ,  Lukas Baumgartel ,  Dan S. Lavric ,  Dax M. Crum ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L27/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.