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公开(公告)号:US20250098249A1
公开(公告)日:2025-03-20
申请号:US18467859
申请日:2023-09-15
Applicant: Intel Corporation
Inventor: Avijit Barik , Tao Chu , Minwoo Jang , Tofizur RAHMAN , Conor P. Puls , Ariana E. Bondoc , Diane Lancaster , Chi-Hing Choi , Derek Keefer
IPC: H01L29/45 , H01L21/285 , H01L23/522 , H01L23/532 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/775 , H01L29/786
Abstract: Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.
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公开(公告)号:US11869889B2
公开(公告)日:2024-01-09
申请号:US16579055
申请日:2019-09-23
Applicant: Intel Corporation
Inventor: Szuya S. Liao , Scott B. Clendenning , Jessica Torres , Lukas Baumgartel , Kiran Chikkadi , Diane Lancaster , Matthew V. Metz , Florian Gstrein , Martin M. Mitan , Rami Hourani
IPC: H01L23/535 , H01L27/088 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L23/538 , H01L27/092
CPC classification number: H01L27/0886 , H01L21/76229 , H01L21/823431 , H01L21/823481 , H01L21/823821 , H01L21/823878 , H01L23/5384 , H01L23/5389 , H01L27/0924 , H01L21/823462 , H01L21/823871
Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
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