公开(公告)号：US12046581B2

公开(公告)日：2024-07-23

申请号：US17723166

申请日：2022-04-18

申请人： Intel Corporation

发明人： Mao Guo ,  Hyoung Il Kim ,  Yong She ,  Sireesha Gogineni

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586

摘要： Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220254757A1

公开(公告)日：2022-08-11

申请号：US17723166

申请日：2022-04-18

申请人： Intel Corporation

发明人： Mao Guo ,  Hyoung Il Kim ,  Yong She ,  Sireesha Gogineni

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

公开(公告)号：US11373974B2

公开(公告)日：2022-06-28

申请号：US16306879

申请日：2016-07-01

申请人： Intel Corporation

发明人： Bilal Khalaf ,  Mao Guo

IPC分类号： H01L23/00 ,  H01L25/065

摘要： Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.

公开(公告)号：US20210280558A1

公开(公告)日：2021-09-09

申请号：US16326650

申请日：2016-09-22

申请人： Intel Corporation

发明人： Mao Guo ,  Hyoung Il Kim ,  Yong She ,  Sireesha Gogineni

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass , and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210074668A1

公开(公告)日：2021-03-11

申请号：US16306879

申请日：2016-07-01

申请人： Intel Corporation

发明人： Bilal Khalaf ,  Mao Guo

IPC分类号： H01L23/00 ,  H01L25/065

摘要： Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.

公开(公告)号：US20190230788A1

公开(公告)日：2019-07-25

申请号：US16336599

申请日：2016-09-30

申请人： Intel Corporation

发明人： Mao Guo

IPC分类号： H05K1/02

摘要： Various examples disclosed relate to a substrate for a semiconductor. The substrate includes a first conducting layer, having a first surface and an opposite second surface. The substrate further includes a second conducting layer extending in a direction substantially parallel to the first conducting layer. The second conducting layer includes a third surface and an opposite fourth surface. A first dielectric layer is disposed between the second surface of the first conducting layer and the third surface of the second conducting layer. The first dielectric layer includes a first dielectric material and a fiber. Slots extends between the first conducting layer and the second conducting layer. Each of the slots is defined by an internal surface of the first conducting layer, the second conducting layer, and the first dielectric layer.

公开(公告)号：US10756072B2

公开(公告)日：2020-08-25

申请号：US15777855

申请日：2015-12-25

申请人： Intel Corporation

发明人： Mao Guo

IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

摘要： A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48) formed on a first foundation layer (12). A loop of conductive wire (50-53) is wirebonded to the first conductive pad ((40, 41, 47, 48) of the first foundation layer (12). A mold cap (70) is formed on the first foundation layer (12). A via (90-93) is formed in the mold cap (70) to reach the conductive wire (50-53). A solder structure (80-83) is coupled to the conductive wire (50-53). A second package (100) is connected to the first package (10) by attaching a second solder structure (110-113) of a second package (100) to the first solder structure (80-83) of the first package (10).

公开(公告)号：US20190229093A1

公开(公告)日：2019-07-25

申请号：US16330056

申请日：2016-10-01

申请人： Intel Corporation

发明人： Juan E. Dominguez ,  Hyoung Il Kim ,  Mao Guo

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/49 ,  H01L23/00 ,  H01L25/00

摘要： Electronic device package technology is disclosed. An electronic device package can comprise a substrate. The electronic device package can also comprise first and second electronic components in a stacked configuration. Each of the first and second electronic components can include an electrical interconnect portion exposed toward the substrate. The electronic device package can further comprise a mold compound encapsulating the first and second electronic components. In addition, the electronic device package can comprise an electrically conductive post extending through the mold compound between the electrical interconnect portion of at least one of the first and second electronic components and the substrate. Associated systems and methods are also disclosed.

公开(公告)号：US10192840B2

公开(公告)日：2019-01-29

申请号：US14866640

申请日：2015-09-25

申请人： Intel Corporation

发明人： Yuhong Cai ,  Mao Guo

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/498

摘要： In some forms, an electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a plurality of lobes projecting distally from a center of the ball pad. In some forms, he electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a lobe projecting distally from a center of the ball pad. In some forms, the electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes at least one lobe projecting distally from a center of the ball pad; and an electronic package that includes at least one conductor that electrically connects the ball pad on the substrate to the electronic package.

公开(公告)号：US10748873B2

公开(公告)日：2020-08-18

申请号：US15755219

申请日：2015-09-23

申请人： Intel Corporation

发明人： Mao Guo ,  Min-Tih Lai ,  Tyler Charles Leuten

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H05K3/46 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

摘要： Substrates, assemblies, and techniques for enabling multi-chip flip chip packages are disclosed herein. For example, in some embodiments, a package substrate may include a first side face; a second side face, wherein the second side face is opposite to the first side face along an axis; a portion of insulating material extending from the first side face to the second side face; wherein a cross-section of the portion of insulating material taken perpendicular to the axis has a stairstep profile. Solder pads may be disposed at base and step surfaces of the portion of insulating material. One or more dies may be coupled to the package substrate (e.g., to form a multi-chip flip chip package), and in some embodiments, additional IC packages may be coupled to the package substrate. In some embodiments, the package substrate may be reciprocally symmetric or approximately reciprocally symmetric.