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34 条记录 (耗时 0.018 秒)

    PACKAGE ON PACKAGE WITH INTEGRATED PASSIVE ELECTRONICS METHOD AND APPARATUS
    1.
    发明申请
    PACKAGE ON PACKAGE WITH INTEGRATED PASSIVE ELECTRONICS METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20190355709A1

    公开(公告)日：2019-11-21

    申请号：US16529348

    申请日：2019-08-01

    申请人： Intel Corporation

    发明人： Hyoung Il Kim

    IPC分类号： H01L25/00 ,  H01L21/56 ,  H01L25/18 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

    摘要： The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.

    SEMICONDUCTOR PACKAGE WITH THERMAL FINS
    2.
    发明申请
    SEMICONDUCTOR PACKAGE WITH THERMAL FINS 审中-公开

    公开(公告)号：US20190067156A1

    公开(公告)日：2019-02-28

    申请号：US15688662

    申请日：2017-08-28

    申请人： Intel Corporation

    发明人： Hyoung Il Kim ,  Florence Pon ,  Yi Xu ,  Yuhong Cai ,  Min-Tih Lai ,  Leo Craft

    IPC分类号： H01L23/367 ,  H01L23/34 ,  H01L23/055 ,  H01L23/14 ,  H01L25/065

    摘要： Embodiments of the present disclosure provide techniques and configurations for a semiconductor package with thermal fins, in accordance with some embodiments. In embodiments, a package assembly may comprise a die and a mold compound disposed on the die, to encapsulate the die. The package may further include a thermal solution comprising one or more thermal fins attached to the mold compound at their respective ends. The thermal fins may be disposed substantially flat on a top surface of the mold compound at a first temperature, and rise away from the top surface of the mold compound in response to a change of temperature to a second temperature, to reach an enclosure that surrounds the package assembly, to provide direct heat conductivity between the die and the enclosure. The second temperature may be greater than the first temperature. Other embodiments may be described and/or claimed.

    Conductive stress-relief washers in microelectronic assemblies
    3.
    发明授权
    Conductive stress-relief washers in microelectronic assemblies 有权

    公开(公告)号：US10120424B2

    公开(公告)日：2018-11-06

    申请号：US15410667

    申请日：2017-01-19

    申请人： Intel Corporation

    发明人： Hyoung Il Kim

    IPC分类号： G06F1/20 ,  H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H01L23/40 ,  G06F1/18 ,  H05K3/36 ,  H01R12/73 ,  H01R12/72 ,  H01R12/70

    摘要： Microelectronic device assembly including a component attached to substrate by at least a screw. The screw applies compressive force against a pad of a thermally and electrically conductive material having sufficiently low modulus to mitigate stress in addition to providing a thermal and electrical path between the component and the substrate. In some embodiments, the screw affixes a printed circuit board hosting one or more integrated circuit components to a motherboard, or passive heat sink. The pad may be deformed to assuage stress applied through the screw during assembly of the device and/or as the device experiences thermal cycling, for example associated with intermittent operation.

    INTEGRATED CIRCUIT PACKAGE WITH GLASS SPACER
    6.
    发明申请
    INTEGRATED CIRCUIT PACKAGE WITH GLASS SPACER 有权

    公开(公告)号：US20220254757A1

    公开(公告)日：2022-08-11

    申请号：US17723166

    申请日：2022-04-18

    申请人： Intel Corporation

    发明人： Mao Guo ,  Hyoung Il Kim ,  Yong She ,  Sireesha Gogineni

    IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L25/00

    摘要： Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

    Semiconductor package with thermal fins
    7.
    发明授权
    Semiconductor package with thermal fins 有权

    公开(公告)号：US10573575B2

    公开(公告)日：2020-02-25

    申请号：US15688662

    申请日：2017-08-28

    申请人： Intel Corporation

    发明人： Hyoung Il Kim ,  Florence Pon ,  Yi Xu ,  Yuhong Cai ,  Min-Tih Lai ,  Leo Craft

    IPC分类号： H01L23/34 ,  H01L23/367 ,  H01L23/055 ,  H01L23/14 ,  H01L25/065

    摘要： Embodiments of the present disclosure provide techniques and configurations for a semiconductor package with thermal fins, in accordance with some embodiments. In embodiments, a package assembly includes a die and a mold compound disposed on the die, to encapsulate the die. The package may further include a thermal solution including one or more thermal fins attached to the mold compound at their respective ends. The thermal fins may be disposed substantially flat on a top surface of the mold compound at a first temperature, and rise away from the top surface of the mold compound in response to a change of temperature to a second temperature, to reach an enclosure that surrounds the package assembly, to provide direct heat conductivity between the die and the enclosure. The second temperature may be greater than the first temperature. Other embodiments may be described and/or claimed.

    MULTI-STACKED DIE PACKAGE WITH FLEXIBLE INTERCONNECT
    8.
    发明申请
    MULTI-STACKED DIE PACKAGE WITH FLEXIBLE INTERCONNECT 审中-公开

    公开(公告)号：US20190333895A1

    公开(公告)日：2019-10-31

    申请号：US16349951

    申请日：2016-12-20

    申请人： Intel Corporation

    发明人： Hyoung Il Kim

    IPC分类号： H01L25/065 ,  H01L23/538

    摘要： An apparatus is provided which comprises: a first die having at least one bond pad; a first flexible layer comprising an anisotropic conductive material, wherein the first flexible layer is adjacent to the at least one bond pad such that it makes an electrical contact with the at least one bond pad; and a second flexible layer comprising a conductive metal, wherein the second flexible layer is adjacent to the first flexible layer.

    Package on package with integrated passive electronics method and apparatus
    9.
    发明授权
    Package on package with integrated passive electronics method and apparatus 有权

    公开(公告)号：US10446533B2

    公开(公告)日：2019-10-15

    申请号：US15721057

    申请日：2017-09-29

    申请人： Intel Corporation

    发明人： Hyoung Il Kim

    IPC分类号： H01L21/00 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L25/18

    摘要： The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.

    Multi-package integrated circuit assembly with through-mold via
    10.
    发明授权
    Multi-package integrated circuit assembly with through-mold via 有权

    公开(公告)号：US10134716B2

    公开(公告)日：2018-11-20

    申请号：US15460982

    申请日：2017-03-16

    申请人： Intel Corporation

    发明人： Hyoung Il Kim

    IPC分类号： H01L25/10 ,  H01L25/00

    摘要： A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A metallic plated hole can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.