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公开(公告)号:US20200006287A1
公开(公告)日:2020-01-02
申请号:US16025710
申请日:2018-07-02
Applicant: Intel Corporation
Inventor: Michael J. HILL , Leigh E. WOJEWODA , Mathew MANUSHAROW , Siddharth KULASEKARAN
IPC: H01L25/065 , H01L49/02 , H01L23/64 , H01L23/34 , H01F27/08
Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein the inductor is at least partially embedded within the substrate. One or more thermal vent structures extend through at least one of the substrate or a board attached to the substrate. The one or more thermal vent structures provide a thermal pathway for cooling for the inductor.
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公开(公告)号:US20200235449A1
公开(公告)日:2020-07-23
申请号:US16841072
申请日:2020-04-06
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Mathew MANUSHAROW , Krishna BHARATH , Zhichao ZHANG , Yidnekachew S. MEKONNEN , Aleksandar ALEKSOV , Henning BRAUNISCH , Feras EID , Javier SOTO
Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
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公开(公告)号:US20180323708A1
公开(公告)日:2018-11-08
申请号:US15772487
申请日:2015-12-22
Applicant: Intel Corporation
Inventor: William J. LAMBERT , Mathew MANUSHAROW
IPC: H02M3/155
CPC classification number: H02M3/155 , H01L25/10 , H05K1/181 , H05K2201/10015 , H05K2201/1003 , H05K2201/10159 , H05K2201/10166 , H05K2201/10522 , H05K2201/10674 , H05K2201/10719
Abstract: A printed circuit board (PCB) includes one or more voltage rails and an integrated voltage regulator (IVR) electrically coupled to supply current to a voltage rail. The PCB also includes a PCB current source electrically coupled to supply a supplementary current to the voltage rail.
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公开(公告)号:US20220231394A1
公开(公告)日:2022-07-21
申请号:US17714957
申请日:2022-04-06
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Mathew MANUSHAROW , Krishna BHARATH , Zhichao ZHANG , Yidnekachew S. MEKONNEN , Aleksandar ALEKSOV , Henning BRAUNISCH , Feras EID , Javier SOTO
Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
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公开(公告)号:US20220093536A1
公开(公告)日:2022-03-24
申请号:US17030121
申请日:2020-09-23
Applicant: Intel Corporation
Inventor: Krishna BHARATH , William J. LAMBERT , Haifa HARIRI , Siddharth KULASEKARAN , Mathew MANUSHAROW , Anne AUGUSTINE
IPC: H01L23/64 , H01L23/00 , H01L23/498 , H01L23/552 , H01L21/48
Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.
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