公开(公告)号：US20220094263A1

公开(公告)日：2022-03-24

申请号：US17030132

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Christopher SCHAEF ,  William J. LAMBERT ,  Kaladhar RADHAKRISHNAN

IPC: H02M3/04 ,  H01F27/24 ,  H01L49/02

Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

公开(公告)号：US20220093565A1

公开(公告)日：2022-03-24

申请号：US17031819

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Krishna BHARATH

IPC: H01L25/065 ,  H01L49/02 ,  H01L23/00 ,  H01L23/64

Abstract: Embodiments disclosed herein include voltage regulators VR integrated into an electronic device. In an embodiment, an electronic device comprises a package substrate, a first die electrically coupled to the package substrate, and a second die with a first surface facing the first die and second surface facing the package substrate that is electrically coupled to the package substrate and the first die. In an embodiment, the second die is between the package substrate and the first die. In an embodiment, the second die comprises voltage regulation (VR) circuitry. In an embodiment current is received by the second die through only the first surface and the current only exits the second die through the second surface.

公开(公告)号：US20200006239A1

公开(公告)日：2020-01-02

申请号：US16024717

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Krishna BHARATH

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/13 ,  H01L51/10 ,  H01L23/367 ,  H01L23/373 ,  H01F27/28 ,  H01L21/48 ,  H01L51/00 ,  H01L23/00

Abstract: Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.

公开(公告)号：US20180331003A1

公开(公告)日：2018-11-15

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Adel A. ELSHERBINI ,  Mihir K. ROY ,  Aleksandar ALEKSOV ,  Yidnekachew S. MEKONNEN ,  Javier SOTO GONZALEZ ,  Feras EID ,  Suddhasattwa NAD ,  Meizi JIAO

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/12 ,  H01L21/486 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20180288868A1

公开(公告)日：2018-10-04

申请号：US15997644

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Matthew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H05K1/02 ,  H01P3/08 ,  H01P3/02

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20230089093A1

公开(公告)日：2023-03-23

申请号：US17482804

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Krishna BHARATH ,  Bharat PENMECHA ,  Anderw COLLINS ,  Kaladhar RADHAKRISHNAN ,  Sriram SRINIVASAN

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a plug is formed through the core, where the plug comprises a magnetic material. In an embodiment, an inductor is around the plug. In an embodiment, first layers are over the core, wherein where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.

公开(公告)号：US20210193583A1

公开(公告)日：2021-06-24

申请号：US17192462

申请日：2021-03-04

Applicant: INTEL CORPORATION

Inventor： Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Shawna M. LIFF ,  Henning BRAUNISCH ,  Krishna BHARATH ,  Javier SOTO GONZALEZ ,  Javier A. FALCON

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L23/498

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US20180315690A1

公开(公告)日：2018-11-01

申请号：US15773030

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew J. MANUSHAROW ,  Krishna BHARATH ,  William J. LAMBERT ,  Robert L. SANKMAN ,  Aleksandar ALEKSOV ,  Brandon M. RAWLINGS ,  Feras EID ,  Javier SOTO GONZALEZ ,  Meizi JIAO ,  Suddhasattwa NAD ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01F27/28 ,  H01L49/02 ,  H01F41/04 ,  H01L21/48 ,  H01G4/33 ,  H01L23/66

CPC classification number: H01F27/40 ,  H01F17/0006 ,  H01L28/00

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20220231394A1

公开(公告)日：2022-07-21

申请号：US17714957

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20220093536A1

公开(公告)日：2022-03-24

申请号：US17030121

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  William J. LAMBERT ,  Haifa HARIRI ,  Siddharth KULASEKARAN ,  Mathew MANUSHAROW ,  Anne AUGUSTINE

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48

Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.