公开(公告)号：US20230253395A1

公开(公告)日：2023-08-10

申请号：US18302063

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L24/02 ,  H01L24/09 ,  H01L23/3107 ,  H01L24/73 ,  H01L24/81 ,  H01L21/568 ,  H01L23/49811 ,  H01L21/4853 ,  H01L24/03 ,  H01L21/6835 ,  H01L24/92 ,  H01L24/96 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/18 ,  H01L25/065 ,  H01L25/105 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L24/48 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/0905 ,  H01L2224/48137 ,  H01L2224/13008 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/45144 ,  H01L23/3114 ,  H01L23/3128 ,  H01L21/561 ,  H01L2224/0401 ,  H01L2224/48091 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/13084 ,  H01L2224/81895 ,  H01L2224/13311 ,  H01L2224/13181 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/03003 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2224/13166 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/45147 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2224/2518 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2224/451 ,  H01L21/304

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

公开(公告)号：US20190115519A1

公开(公告)日：2019-04-18

申请号：US16091125

申请日：2017-03-24

Applicant: DENSO CORPORATION

Inventor： Takuya MATSUDA ,  Shinya KITAGAWA ,  Yoshiyuki OKAMOTO

IPC: H01L35/30 ,  H01L35/32

CPC classification number: H01L35/30 ,  F28F3/025 ,  F28F3/027 ,  F28F2215/04 ,  F28F2215/08 ,  H01L23/10 ,  H01L23/467 ,  H01L23/473 ,  H01L25/10 ,  H01L35/32 ,  H02N11/00

Abstract: A thermoelectric generator includes a tube in which a first fluid flows, a power generation module, a holding member, and a heat exchanging fin. The power generation module includes a thermoelectric conversion element. The holding member holds a stacked body in which the power generation module and the tube are stacked with each other such that heat can be transferred between the power generation module and the tube. Both end portions of the holding member are located and fixed outside both ends of the stacked body. The heat exchanging fin includes a pair of end fin portions provided on the reverse surface of the holding member at portions corresponding to the both ends of the stacked body, and an intermediate fin located between the pair of end fin portions and higher in stiffness than the pair of end fin portions.

公开(公告)号：US20180082916A1

公开(公告)日：2018-03-22

申请号：US15827550

申请日：2017-11-30

Applicant: Invensas Corporation

Inventor： Rajesh Katkar

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/10 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83005 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly. into microelectronic units, each including a microelectronic element. The surface of the microelectronic unit, opposite the redistribution structure, having both the active face of the microelectronic element and the free ends of the connector elements so that both are available for connection with a component external to the microelectronic unit.

公开(公告)号：US09761534B2

公开(公告)日：2017-09-12

申请号：US15162760

申请日：2016-05-24

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L25/065 ,  H01L25/16 ,  H01L23/50 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.

公开(公告)号：US09721852B2

公开(公告)日：2017-08-01

申请号：US14159449

申请日：2014-01-21

Applicant: International Business Machines Corporation

Inventor： Richard Stephen Graf ,  David Justin West

IPC: H01L23/02 ,  H01L21/66 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L22/10 ,  H01L21/565 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/83 ,  H01L25/10 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV) layer including a first logic die and TSVs. The logic circuit-TSV layer is within the overmold layer, and the TSVs are electrically exposed at a top surface of the overmold layer. The first package may be fabricated and tested by a first party prior to being provided to a second party. A second package includes a second logic die. The second party may attach the second package to the first package at the electrically exposed TSVs of the first package to realize a complete and functional semiconductor device.

公开(公告)号：US09692100B2

公开(公告)日：2017-06-27

申请号：US14823054

申请日：2015-08-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takahiro Baba ,  Nobuo Ikemoto

IPC: H01P3/08 ,  H05K1/02 ,  H01L25/10 ,  H01L25/18 ,  H05K1/14

CPC classification number: H01P3/085 ,  H01L25/10 ,  H01L25/18 ,  H01L2924/0002 ,  H01P3/08 ,  H01P3/082 ,  H05K1/0225 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/147 ,  H05K2201/09727 ,  H01L2924/00

Abstract: A flat cable includes a plurality of resin layers that are flexible and stacked together, a line conductor, and grounding conductors. The flat cable includes a triplate line in which both surfaces of the line conductor oppose the corresponding grounding conductors, and a microstrip line in which only one of the surfaces of the line conductor opposes the corresponding grounding conductor. A width of the line conductor in the microstrip line is greater than a width of the line conductor in the triplate line, and the flat cable is bent at a position where the microstrip line is provided.

公开(公告)号：US09613938B2

公开(公告)日：2017-04-04

申请号：US14987892

申请日：2016-01-05

Applicant: Soichiro Suzu ,  Tomohito Taki

Inventor： Soichiro Suzu ,  Tomohito Taki

IPC: H05K1/18 ,  H01L25/10 ,  H01L23/043 ,  H01L21/54 ,  H01L23/00 ,  H01L25/00 ,  H01L23/16

CPC classification number: H01L25/10 ,  H01L21/54 ,  H01L23/043 ,  H01L23/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/29191 ,  H01L2224/3013 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48135 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49051 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A module includes a first substrate including first electrodes; a first element bonded to the first substrate, and including second electrodes disposed at a first end of the first element and third electrodes disposed at a second end of the first element opposite from the first end; a second substrate stacked on the first substrate and including a recess; and a second element bonded to a bottom surface of the recess of the second substrate and including fourth electrodes. The first electrodes of the first substrate are electrically connected to the second electrodes at the first end of the first element, and the third electrodes at the second end of the first element are electrically connected to the fourth electrodes of the second element via a through hole formed in the bottom surface of the recess.

公开(公告)号：US09559085B2

公开(公告)日：2017-01-31

申请号：US14423693

申请日：2012-09-11

Applicant: Seng-Teong Chang ,  Choon Keat Or ,  Wai-Choo Chai ,  Chong-Tee Ong

Inventor： Seng-Teong Chang ,  Choon Keat Or ,  Wai-Choo Chai ,  Chong-Tee Ong

IPC: H01L21/00 ,  H01L25/13 ,  H01L25/075 ,  H01L33/54 ,  H01L33/56 ,  H01L21/48 ,  H01L25/10 ,  H01L31/02 ,  H01L31/0203 ,  H01L33/48 ,  H01L33/62

CPC classification number: H01L25/13 ,  H01L21/4803 ,  H01L25/0753 ,  H01L25/0756 ,  H01L25/10 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L33/54 ,  H01L33/56 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/005 ,  H01L2933/0066 ,  H01L2924/00

Abstract: A method for producing an optoelectronic device is specified. A housing base body is formed with a self-healing polymer material. A recess is found in the housing base body. The recess is confined by a bottom surface and at least one side wall which are formed at least in places by the plastic material of the base body. An optoelectronic semiconductor chip has a first main surface, a second main surface facing away from the first main surface and at least one side surface connecting the first main surface and the second main surface with each other. The optoelectronic semiconductor chip is placed in the recess, so that the first main surface is brought in contact with the bottom surface and the at least one side surface is brought in contact with the at least one side wall.

Abstract translation: 规定了光电器件的制造方法。 壳体基体形成有自修复聚合物材料。 在壳体基体中发现凹陷。 该凹部由底面和至少一个侧壁限制，至少一个侧壁至少由基体的塑料材料形成。 光电子半导体芯片具有第一主表面，远离第一主表面的第二主表面和将第一主表面和第二主表面彼此连接的至少一个侧表面。 将光电子半导体芯片放置在凹部中，使得第一主表面与底表面接触，并且至少一个侧表面与至少一个侧壁接触。

公开(公告)号：US09559081B1

公开(公告)日：2017-01-31

申请号：US14935310

申请日：2015-11-06

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7684 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/181 ,  H01L2924/186

Abstract: Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.

Abstract translation: 描述了封装和3D裸片堆叠过程。 在一个实施例中，封装包括结合到包括封装在氧化物层中的第一级管芯的第一封装级的第二级管芯晶体管和延伸穿过氧化物层的多个通孔氧化物通孔（TOV）。 在一个实施例中，TOV和第一级模具具有大约20微米或更小的高度。

公开(公告)号：US09548289B2

公开(公告)日：2017-01-17

申请号：US14741796

申请日：2015-06-17

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ming-Tzong Yang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H01L25/18 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H05K1/112 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括其上具有第一焊盘的第一半导体管芯。 第一通孔设置在第一半导体管芯上，耦合到第一焊盘。 第一动态随机存取存储器（DRAM）管芯安装在第一半导体管芯上，耦合到第一通孔。 第二半导体封装堆叠在第一半导体封装上。 第二半导体封装包括具有管芯附接表面和与管芯附接表面相对的凸起附着表面的主体。 第二动态随机存取存储器（DRAM）裸片安装在芯片附接表面上，通过接合线耦合到主体。 第一DRAM裸片的输入/输出（I / O）引脚的数量与第二DRAM裸片的输入/输出（I / O）引脚的数量不同。