公开(公告)号：US20220102055A1

公开(公告)日：2022-03-31

申请号：US17033354

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Krishna BHARATH ,  Haifa HARIRI ,  Tarek A. IBRAHIM

IPC: H01F27/28 ,  H01L23/498 ,  H01L23/64 ,  H01F41/04 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages with embedded inductors and methods of forming such electronic packages. In an embodiment, the electronic package comprises a package core, and a plated through hole (PTH) through a thickness of the package core. In an embodiment, the electronic package further and a magnetic shell around a perimeter of the PTH, where a height of the magnetic shell is less than the thickness of the package core. In an embodiment, the magnetic shell comprises a substantially vertical sidewall and a bottom surface that is tapered.

公开(公告)号：US20250113434A1

公开(公告)日：2025-04-03

申请号：US18374617

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Bai NIE ,  Mitchell PAGE ,  Junxin WANG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Haifa HARIRI ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Hongxia FENG ,  Haobo CHEN ,  Bohan SHAN ,  Hiroki TANAKA ,  Leonel R. ARANA ,  Yonggang Yong LI

IPC: H05K1/02 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. In an embodiment a corner at a junction between the sidewall and the first surface is rounded. In an embodiment, a via is provided in the opening, where the via is electrically conductive.

公开(公告)号：US20200294920A1

公开(公告)日：2020-09-17

申请号：US16299415

申请日：2019-03-12

Applicant: Intel Corporation

Inventor： Haifa HARIRI ,  Amruthavalli P. ALUR ,  Wei-Lun K. JEN ,  Islam A. SALAMA

IPC: H01L23/538 ,  H01L23/31

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.

公开(公告)号：US20240105575A1

公开(公告)日：2024-03-28

申请号：US17953206

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Jason M. GAMBA ,  Haifa HARIRI ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Kyle MCELHINNY ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Haobo CHEN ,  Bai NIE ,  Numair AHMED

IPC: H01L23/498 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48

CPC classification number: H01L23/49838 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/123 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49866 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.

公开(公告)号：US20220093536A1

公开(公告)日：2022-03-24

申请号：US17030121

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  William J. LAMBERT ,  Haifa HARIRI ,  Siddharth KULASEKARAN ,  Mathew MANUSHAROW ,  Anne AUGUSTINE

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48

Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

公开(公告)号：US20210305138A1

公开(公告)日：2021-09-30

申请号：US16828466

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Zhenguo JIANG ,  Haifa HARIRI ,  Kemal AYGÜN ,  Sriram SRINIVASAN

IPC: H01L23/498 ,  H01R12/71

Abstract: Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end.