公开(公告)号：US11703927B2

公开(公告)日：2023-07-18

申请号：US16833328

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Oren Zonensain ,  Roman Rechter ,  Almog Reshef ,  Maxim Levit ,  Nadav Shulman ,  Efraim Rotem

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/28 ,  G01R31/52

CPC classification number: G06F1/28 ,  G01R31/52

Abstract: A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

公开(公告)号：US20200225723A1

公开(公告)日：2020-07-16

申请号：US16833328

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Oren Zonensain ,  Roman Rechter ,  Almog Reshef ,  Maxim Levit ,  Nadav Shulman ,  Efraim Rotem

IPC: G06F1/28 ,  G01R31/52

Abstract: A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

公开(公告)号：US09983644B2

公开(公告)日：2018-05-29

申请号：US14936945

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Shmuel Zobel ,  Maxim Levit ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.

公开(公告)号：US09933477B2

公开(公告)日：2018-04-03

申请号：US14228728

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Shmuel Zobel ,  Maxim Levit

IPC: G01R31/3187 ,  G01R31/26 ,  G05F1/56 ,  G06F1/26

CPC classification number: G01R31/2642 ,  G01R31/2608 ,  G05F1/56 ,  G06F1/26 ,  G06F1/3243

Abstract: A method is described that includes monitoring degradation of a semiconductor chip's transistors during normal operation. The method further includes raising an internal voltage of the semiconductor chip in response to the degradation. The method further includes determining that the degradation has reached a threshold. The method further includes triggering application of an elevated temperature to the semiconductor chip so that the degradation is at least partially reversed. The method further includes applying a new lower internal voltage of the semiconductor chip in account of the degradation reversal.

公开(公告)号：US20170131754A1

公开(公告)日：2017-05-11

申请号：US14936945

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Shmuel Zobel ,  Maxim Levit ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.